467 lines
11 KiB
Plaintext
467 lines
11 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0 OR X11
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/*
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* Copyright (C) 2015 Amarula Solutions B.V.
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* Copyright (C) 2015 Engicam S.r.l.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/sound/fsl-imx-audmux.h>
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/ {
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x80000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "1P8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_2p5v: regulator-2p5v {
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compatible = "regulator-fixed";
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regulator-name = "2P5V";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_sd3_vmmc: regulator-sd3-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "P3V3_SD3_SWITCHED";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
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enable-active-high;
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};
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reg_sd4_vmmc: regulator-sd4-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "P3V3_SD4_SWITCHED";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_usb_h1_vbus: regulator-usb-h1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_h1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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usb_hub: usb-hub {
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compatible = "smsc,usb3503a";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbhub>;
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reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
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clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
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clock-names = "refclk";
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,widgets =
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"Microphone", "Mic Jack",
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"Headphone", "Headphone Jack",
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"Line", "Line In Jack",
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"Speaker", "Line Out Jack",
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"Speaker", "Ext Spk";
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simple-audio-card,routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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simple-audio-card,cpu {
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sound-dai = <&ssi1>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&sgtl5000>;
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};
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};
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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status = "okay";
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audmux_ssi1 {
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fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
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fsl,port-config = <
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(IMX_AUDMUX_V2_PTCR_TFSDIR |
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IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
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IMX_AUDMUX_V2_PTCR_TCLKDIR |
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IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
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IMX_AUDMUX_V2_PTCR_SYN)
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IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
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>;
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};
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audmux_aud4 {
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fsl,audmux-port = <MX51_AUDMUX_PORT4>;
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fsl,port-config = <
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IMX_AUDMUX_V2_PTCR_SYN
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IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
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>;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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xceiver-supply = <®_3p3v>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2>;
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xceiver-supply = <®_3p3v>;
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status = "okay";
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-handle = <ð_phy>;
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phy-mode = "rgmii";
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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eth_phy: ethernet-phy@0 {
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reg = <0x0>;
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rxc-skew-ps = <1140>;
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txc-skew-ps = <1140>;
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txen-skew-ps = <600>;
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rxdv-skew-ps = <240>;
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rxd0-skew-ps = <420>;
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rxd1-skew-ps = <600>;
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rxd2-skew-ps = <420>;
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rxd3-skew-ps = <240>;
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txd0-skew-ps = <60>;
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txd1-skew-ps = <60>;
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txd2-skew-ps = <60>;
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txd3-skew-ps = <240>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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sgtl5000: codec@a {
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#sound-dai-cells = <0>;
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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VDDA-supply = <®_2p5v>;
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VDDIO-supply = <®_3p3v>;
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VDDD-supply = <®_1p8v>;
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&ssi1 {
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fsl,mode = "i2s-slave";
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&usbh1 {
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vbus-supply = <®_usb_h1_vbus>;
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disable-over-current;
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clocks = <&clks IMX6QDL_CLK_USBOH3>;
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status = "okay";
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};
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&usbotg {
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vbus-supply = <®_usb_otg_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg>;
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disable-over-current;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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vmcc-supply = <®_sd3_vmmc>;
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cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc4 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc4>;
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pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
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vmcc-supply = <®_sd4_vmmc>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_audmux: audmuxgrp {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
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MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
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MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
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MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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>;
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};
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pinctrl_can1: can1grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
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MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
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>;
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};
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pinctrl_can2: can2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
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MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
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>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pcie: pciegrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart4: uart4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbhub: usbhubgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg: usbotggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
|
||
|
|
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
|
||
|
|
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
|
||
|
|
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
|
||
|
|
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
|
||
|
|
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
|
||
|
|
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */
|
||
|
|
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc4: usdhc4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
|
||
|
|
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
|
||
|
|
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
|
||
|
|
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
|
||
|
|
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
|
||
|
|
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
|
||
|
|
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
|
||
|
|
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
|
||
|
|
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
|
||
|
|
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1
|
||
|
|
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
|
||
|
|
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9
|
||
|
|
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
|
||
|
|
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|