429 lines
9.3 KiB
Plaintext
429 lines
9.3 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Digi International's ConnectCore6UL SBC Pro board device tree source
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*
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* Copyright 2018 Digi International, Inc.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6ul.dtsi"
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#include "imx6ul-ccimx6ulsom.dtsi"
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/ {
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model = "Digi International ConnectCore 6UL SBC Pro.";
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compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";
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lcd_backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm5 0 50000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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status = "okay";
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};
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panel {
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compatible = "auo,g101evn010";
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power-supply = <&ldo4_ext>;
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backlight = <&lcd_backlight>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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reg_usb_otg1_vbus: regulator-usb-otg1 {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&adc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc1>;
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <&ext_3v3>;
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status = "okay";
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};
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/* CAN2 is multiplexed with UART2 RTS/CTS */
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <&ext_3v3>;
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status = "disabled";
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};
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&ecspi1 {
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cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1_master>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <26>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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smsc,disable-energy-detect;
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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smsc,disable-energy-detect;
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reg = <1>;
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};
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};
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};
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&gpio5 {
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emmc-usd-mux-hog {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_LOW>;
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output-high;
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};
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};
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&i2c1 {
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touchscreen@14 {
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compatible = "goodix,gt911";
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reg = <0x14>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_goodix_touch>;
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interrupt-parent = <&gpio5>;
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interrupts = <2 IRQ_TYPE_EDGE_RISING>;
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irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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};
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&lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif_dat0_17
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&pinctrl_lcdif_clken
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&pinctrl_lcdif_hvsync>;
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lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */
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status = "okay";
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port {
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display_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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&ldo4_ext {
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regulator-max-microvolt = <1800000>;
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};
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&pwm1 {
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status = "okay";
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};
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&pwm2 {
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status = "okay";
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};
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&pwm3 {
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status = "okay";
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};
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&pwm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm4>;
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status = "okay";
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};
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&pwm5 {
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm5>;
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status = "okay";
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};
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&pwm6 {
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status = "okay";
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};
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&pwm7 {
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status = "okay";
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};
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&pwm8 {
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status = "okay";
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};
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&sai2 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_sai2>;
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pinctrl-1 = <&pinctrl_sai2_sleep>;
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assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
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<&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
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<&clks IMX6UL_CLK_SAI2>;
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assigned-clock-rates = <0>, <786432000>, <12288000>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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status = "okay";
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};
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/* UART2 RTS/CTS muxed with CAN2 */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_4wires>;
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uart-has-rtscts;
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status = "okay";
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};
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/* UART3 RTS/CTS muxed with CAN 1 */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3_2wires>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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vbus-supply = <®_usb_otg1_vbus>;
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pinctrl-0 = <&pinctrl_usbotg1>;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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/* USDHC2 (microSD conflicts with eMMC) */
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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no-1-8-v;
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broken-cd; /* no carrier detect line (use polling) */
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status = "okay";
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};
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&iomuxc {
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pinctrl_adc1: adc1grp {
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fsl,pins = <
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/* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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>;
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};
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pinctrl_ecspi1_master: ecspi1grp1 {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0
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MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0
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MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0
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MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051
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>;
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};
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pinctrl_enet2_mdio: mdioenet2grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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>;
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};
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pinctrl_flexcan1: flexcan1grp{
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fsl,pins = <
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MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
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MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
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>;
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};
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pinctrl_flexcan2: flexcan2grp{
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fsl,pins = <
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MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
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MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
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>;
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};
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pinctrl_goodix_touch: goodixgrp{
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020
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>;
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};
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pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
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MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
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MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
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MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
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MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
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MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
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MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
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MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
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MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
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MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
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MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
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MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
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MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
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MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
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MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
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MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
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MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
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MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
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>;
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};
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pinctrl_lcdif_clken: lcdifctrlgrp1 {
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fsl,pins = <
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MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050
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MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
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>;
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};
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pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
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fsl,pins = <
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MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
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MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
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>;
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};
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pinctrl_pwm4: pwm4grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
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>;
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};
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pinctrl_pwm5: pwm5grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_sai2: sai2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
|
||
|
|
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
|
||
|
|
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
|
||
|
|
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
||
|
|
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
||
|
|
/* Interrupt */
|
||
|
|
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_sai2_sleep: sai2grp-sleep {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000
|
||
|
|
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000
|
||
|
|
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000
|
||
|
|
MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000
|
||
|
|
/* Interrupt */
|
||
|
|
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2_4wires: uart2grp-4wires {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
|
||
|
|
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
|
||
|
|
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
|
||
|
|
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart3_2wires: uart3grp-2wires {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
|
||
|
|
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart5: uart5grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
|
||
|
|
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
|
||
|
|
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039
|
||
|
|
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
|
||
|
|
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
|
||
|
|
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
|
||
|
|
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
|
||
|
|
/* Mux selector between eMMC/SD# */
|
||
|
|
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg1: usbotg1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
||
|
|
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059
|
||
|
|
MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|