263 lines
6.5 KiB
Plaintext
263 lines
6.5 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2023 DH electronics GmbH
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*/
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/regulator/dlg,da9063-regulator.h>
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#include "imx6ull.dtsi"
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/ {
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memory@80000000 {
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/* Appropriate memory size will be filled by U-Boot */
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reg = <0x80000000 0>;
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device_type = "memory";
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};
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};
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&cpu0 {
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/*
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* Due to the design as a solderable SOM, there are no capacitors
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* below the SoC, therefore higher voltages are required.
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*/
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operating-points = <
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/* kHz uV */
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900000 1275000
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792000 1250000 /* Voltage increased */
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528000 1175000
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396000 1025000
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198000 950000
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>;
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fsl,soc-operating-points = <
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/* KHz uV */
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900000 1250000
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792000 1250000 /* Voltage increased */
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528000 1175000
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396000 1175000
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198000 1175000
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>;
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};
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&gpio1 {
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pinctrl-0 = <&pinctrl_spi1_switch>;
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pinctrl-names = "default";
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/*
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* Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the
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* DHCOM SPI1 interface or accessing the SPI bootflash. Both using
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* ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
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* the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins
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* PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for
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* DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they
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* are used for the bus interface to the SPI bootflash. The GPIOs are
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* disconnected by a buffer which is also controlled via the pin
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* SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a
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* special case and is disabled by setting GPIO 1.9 to high.
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*/
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spi1-switch-hog {
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gpio-hog;
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gpios = <9 0>;
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output-high;
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line-name = "spi1-switch";
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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pinctrl-names = "default", "gpio";
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scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pmic@58 {
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compatible = "dlg,da9061";
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reg = <0x58>;
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onkey {
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compatible = "dlg,da9061-onkey", "dlg,da9062-onkey";
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status = "disabled";
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};
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regulators {
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vdd_soc_in_1v4: buck1 {
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regulator-allowed-modes = <DA9063_BUCK_MODE_SLEEP>; /* PFM */
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regulator-always-on;
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regulator-boot-on;
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regulator-initial-mode = <DA9063_BUCK_MODE_SLEEP>;
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regulator-max-microvolt = <1400000>;
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regulator-min-microvolt = <1400000>;
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regulator-name = "vdd_soc_in_1v4";
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};
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vcc_3v3: buck2 {
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regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
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regulator-always-on;
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regulator-boot-on;
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regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "vcc_3v3";
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};
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/*
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* The current DRR3 memory can be supplied with a
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* voltage of either 1.35V or 1.5V. For reasons of
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* backward compatibility to only 1.5V DDR3 memory,
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* the voltage is set to 1.5V.
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*/
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vcc_ddr_1v35: buck3 {
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regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
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regulator-always-on;
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regulator-boot-on;
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regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
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regulator-max-microvolt = <1500000>;
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regulator-min-microvolt = <1500000>;
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regulator-name = "vcc_ddr_1v35";
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};
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vcc_2v5: ldo1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <2500000>;
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regulator-min-microvolt = <2500000>;
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regulator-name = "vcc_2v5";
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};
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vdd_snvs_in_3v3: ldo2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "vdd_snvs_in_3v3";
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};
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vcc_1v8: ldo3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "vcc_1v8";
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};
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vcc_1v2: ldo4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1200000>;
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regulator-min-microvolt = <1200000>;
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regulator-name = "vcc_1v2";
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};
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};
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thermal {
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compatible = "dlg,da9061-thermal", "dlg,da9062-thermal";
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status = "disabled";
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};
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watchdog {
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compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
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status = "disabled";
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};
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};
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};
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&ocotp {
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/* Don't get write access by default */
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read-only;
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};
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®_arm {
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vin-supply = <&vdd_soc_in_1v4>;
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};
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®_soc {
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vin-supply = <&vdd_soc_in_1v4>;
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};
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/* BT on LGA (BT_REG_ON is connected to LGA pin E1) */
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&uart2 {
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pinctrl-0 = <&pinctrl_uart2>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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/*
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* Actually, the maximum speed of the chip is 4MBdps, but there are
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* limitations that prevent this speed. It hasn't yet been figured out
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* what the reason for this is. Currently, the maximum speed of 3MBdps
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* can be used without any problems. If the limitation can be overcome,
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* the speed can be increased accordingly.
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*/
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bluetooth: bluetooth {
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compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */
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max-speed = <3000000>;
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vbat-supply = <&vcc_3v3>;
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vddio-supply = <&vcc_3v3>;
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};
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};
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/* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */
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&usdhc1 {
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#address-cells = <1>;
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#size-cells = <0>;
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bus-width = <4>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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pinctrl-0 = <&pinctrl_usdhc1_wifi>;
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pinctrl-names = "default";
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wakeup-source;
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status = "okay";
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brcmf: wifi@1 {
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compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */
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reg = <1>;
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};
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};
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&iomuxc {
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pinctrl_i2c1: i2c1-grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c1_gpio: i2c1-gpio-grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
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>;
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};
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pinctrl_spi1_switch: spi1-switch-grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x120b0 /* SPI_BOOT_FLASH_EN */
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>;
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};
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pinctrl_uart2: uart2-grp {
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fsl,pins = <
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MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
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MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
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MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
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MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
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>;
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};
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pinctrl_usdhc1_wifi: usdhc1-wifi-grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1b0b0
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10010
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x1b0b0
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x1b0b0
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x1b0b0
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x1b0b0
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>;
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};
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};
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