469 lines
11 KiB
Plaintext
469 lines
11 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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//
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// Copyright (C) 2020 PHYTEC Messtechnik GmbH
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// Author: Jens Lang <J.Lang@phytec.de>
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// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx7d.dtsi"
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/ {
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model = "Storopack SMEGW01 board";
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compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
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aliases {
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mmc0 = &usdhc1;
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mmc1 = &usdhc3;
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mmc2 = &usdhc2;
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rtc0 = &i2c_rtc;
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rtc1 = &snvs_rtc;
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};
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chosen {
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stdout-path = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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reg_lte_on: regulator-lte-on {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lte_on>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "lte_on";
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gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_lte_nreset: regulator-lte-nreset {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lte_nreset>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "LTE_nReset";
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gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_wifi: regulator-wifi {
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compatible = "regulator-fixed";
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gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wifi>;
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regulator-name = "wifi_reg";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_wlan_rfkill: regulator-wlan-rfkill {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-2 = <&pinctrl_rfkill>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "wlan_rfkill";
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gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_usbotg_vbus: regulator-usbotg-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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status = "okay";
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sram@0 {
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compatible = "microchip,48l640";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <16000000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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reg = <1>;
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reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
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};
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ethphy1: ethernet-phy@2 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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reg = <2>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 =<&pinctrl_i2c2>;
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clock-frequency = <100000>;
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status = "okay";
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i2c_rtc: rtc@52 {
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compatible = "microcrystal,rv3028";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rtc_int>;
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reg = <0x52>;
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interrupt-parent = <&gpio2>;
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interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
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dr_mode = "otg";
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vbus-supply = <®_usbotg_vbus>;
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status = "okay";
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};
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&usbotg2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg2>;
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over-current-active-low;
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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wakeup-source;
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keep-power-in-suspend;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <4>;
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no-1-8-v;
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non-removable;
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vmmc-supply = <®_wifi>;
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wakeup-source;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
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max-frequency = <200000000>;
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bus-width = <8>;
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fsl,tuning-step = <1>;
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non-removable;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-hs200-1_8v;
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mmc-ddr-1_8v;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
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MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
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MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
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MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
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MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
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MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
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MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
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MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
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MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
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MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
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MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
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MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
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MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
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MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
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MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
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MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
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MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
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MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
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MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
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MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
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MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
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>;
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};
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pinctrl_lte_on: lteongrp {
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fsl,pins = <
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MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
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>;
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};
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pinctrl_lte_nreset: ltenresetgrp {
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fsl,pins = <
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MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
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>;
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};
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pinctrl_rfkill: rfkillrp {
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fsl,pins = <
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MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
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>;
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};
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pinctrl_rtc_int: rtcintgrp {
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fsl,pins = <
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MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
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>;
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};
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|
pinctrl_uart1: uart1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
|
||
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart3: uart3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
|
||
|
|
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg1_lpsr: usbotg1 {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg1_pwr: usbotg1-pwr {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg2: usbotg2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x5c
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
|
||
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
||
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
||
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
||
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
||
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
||
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
|
||
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
||
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
|
||
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
|
||
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
|
||
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
|
||
|
|
MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
|
||
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
|
||
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
|
||
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
|
||
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
|
||
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
|
||
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
|
||
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
|
||
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
|
||
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
|
||
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
|
||
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
|
||
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
|
||
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
|
||
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
|
||
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
|
||
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
|
||
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
|
||
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
|
||
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
|
||
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
|
||
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
|
||
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
|
||
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
|
||
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
|
||
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
|
||
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
|
||
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
|
||
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
|
||
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
|
||
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wifi: wifigrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
|
||
|
|
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&iomuxc_lpsr {
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|