74 lines
1.2 KiB
Plaintext
74 lines
1.2 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2014 Carlo Caione <carlo@caione.org>
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*/
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#include "meson.dtsi"
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/ {
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model = "Amlogic Meson6 SoC";
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compatible = "amlogic,meson6";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x200>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x201>;
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};
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};
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apb2: bus@d0000000 {
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compatible = "simple-bus";
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reg = <0xd0000000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xd0000000 0x40000>;
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};
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clk81: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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}; /* end of / */
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&efuse {
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status = "disabled";
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};
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&timer_abcde {
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clocks = <&xtal>, <&clk81>;
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clock-names = "xtal", "pclk";
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};
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&uart_AO {
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clocks = <&xtal>, <&clk81>, <&clk81>;
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clock-names = "xtal", "pclk", "baud";
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};
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&uart_A {
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clocks = <&xtal>, <&clk81>, <&clk81>;
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clock-names = "xtal", "pclk", "baud";
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};
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&uart_B {
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clocks = <&xtal>, <&clk81>, <&clk81>;
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clock-names = "xtal", "pclk", "baud";
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};
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&uart_C {
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clocks = <&xtal>, <&clk81>, <&clk81>;
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clock-names = "xtal", "pclk", "baud";
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};
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