517 lines
13 KiB
Plaintext
517 lines
13 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Marvell Technology Group Ltd.
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* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
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*/
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#include <dt-bindings/clock/marvell,mmp2.h>
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#include <dt-bindings/power/marvell,mmp2.h>
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#include <dt-bindings/clock/marvell,mmp2-audio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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i2c0 = &twsi1;
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i2c1 = &twsi2;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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L2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0x3>;
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};
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axi@d4200000 { /* AXI */
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compatible = "mrvl,axi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd4200000 0x00200000>;
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ranges;
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gpu: gpu@d420d000 {
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compatible = "vivante,gc";
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reg = <0xd420d000 0x4000>;
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interrupts = <8>;
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status = "disabled";
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clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
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<&soc_clocks MMP2_CLK_GPU_BUS>;
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clock-names = "core", "bus";
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power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
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};
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intc: interrupt-controller@d4282000 {
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compatible = "mrvl,mmp2-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xd4282000 0x1000>;
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mrvl,intc-nr-irqs = <64>;
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};
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intcmux4: interrupt-controller@d4282150 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x150 0x4>, <0x168 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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intcmux5: interrupt-controller@d4282154 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <5>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x154 0x4>, <0x16c 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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mrvl,clr-mfp-irq = <1>;
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};
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intcmux9: interrupt-controller@d4282180 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <9>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x180 0x4>, <0x17c 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <3>;
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};
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intcmux17: interrupt-controller@d4282158 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <17>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x158 0x4>, <0x170 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <5>;
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};
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intcmux35: interrupt-controller@d428215c {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <35>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x15c 0x4>, <0x174 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <15>;
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};
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intcmux51: interrupt-controller@d4282160 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <51>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x160 0x4>, <0x178 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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intcmux55: interrupt-controller@d4282188 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <55>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x188 0x4>, <0x184 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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usb_phy0: usb-phy@d4207000 {
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compatible = "marvell,mmp2-usb-phy";
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reg = <0xd4207000 0x40>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_otg0: usb-otg@d4208000 {
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compatible = "marvell,pxau2o-ehci";
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reg = <0xd4208000 0x200>;
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interrupts = <44>;
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clocks = <&soc_clocks MMP2_CLK_USB>;
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clock-names = "USBCLK";
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phys = <&usb_phy0>;
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phy-names = "usb";
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status = "disabled";
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};
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mmc1: mmc@d4280000 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0xd4280000 0x120>;
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clocks = <&soc_clocks MMP2_CLK_SDH0>;
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clock-names = "io";
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interrupts = <39>;
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status = "disabled";
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};
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mmc2: mmc@d4280800 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0xd4280800 0x120>;
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clocks = <&soc_clocks MMP2_CLK_SDH1>;
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clock-names = "io";
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interrupts = <52>;
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status = "disabled";
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};
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mmc3: mmc@d4281000 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0xd4281000 0x120>;
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clocks = <&soc_clocks MMP2_CLK_SDH2>;
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clock-names = "io";
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interrupts = <53>;
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status = "disabled";
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};
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mmc4: mmc@d4281800 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0xd4281800 0x120>;
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clocks = <&soc_clocks MMP2_CLK_SDH3>;
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clock-names = "io";
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interrupts = <54>;
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status = "disabled";
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};
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camera0: camera@d420a000 {
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compatible = "marvell,mmp2-ccic";
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reg = <0xd420a000 0x800>;
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interrupts = <42>;
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clocks = <&soc_clocks MMP2_CLK_CCIC0>;
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clock-names = "axi";
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#clock-cells = <0>;
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clock-output-names = "mclk";
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status = "disabled";
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};
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camera1: camera@d420a800 {
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compatible = "marvell,mmp2-ccic";
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reg = <0xd420a800 0x800>;
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interrupts = <30>;
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clocks = <&soc_clocks MMP2_CLK_CCIC1>;
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clock-names = "axi";
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#clock-cells = <0>;
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clock-output-names = "mclk";
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status = "disabled";
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};
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adma0: dma-controller@d42a0800 {
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compatible = "marvell,adma-1.0";
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reg = <0xd42a0800 0x100>;
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interrupts = <48>;
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#dma-cells = <1>;
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asram = <&asram>;
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iram = <&asram>;
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status = "disabled";
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};
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adma1: dma-controller@d42a0900 {
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compatible = "marvell,adma-1.0";
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reg = <0xd42a0900 0x100>;
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interrupts = <48>;
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#dma-cells = <1>;
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status = "disabled";
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};
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audio_clk: clocks@d42a0c30 {
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compatible = "marvell,mmp2-audio-clock";
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reg = <0xd42a0c30 0x10>;
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clock-names = "audio", "vctcxo", "i2s0", "i2s1";
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clocks = <&soc_clocks MMP2_CLK_AUDIO>,
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<&soc_clocks MMP2_CLK_VCTCXO>,
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<&soc_clocks MMP2_CLK_I2S0>,
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<&soc_clocks MMP2_CLK_I2S1>;
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power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
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#clock-cells = <1>;
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status = "disabled";
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};
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sspa0: audio-controller@d42a0c00 {
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compatible = "marvell,mmp-sspa";
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reg = <0xd42a0c00 0x30>,
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<0xd42a0c80 0x30>;
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interrupts = <2>;
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clock-names = "audio", "bitclk";
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clocks = <&soc_clocks MMP2_CLK_AUDIO>,
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<&audio_clk MMP2_CLK_AUDIO_SSPA0>;
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power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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sspa1: audio-controller@d42a0d00 {
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compatible = "marvell,mmp-sspa";
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reg = <0xd42a0d00 0x30>,
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<0xd42a0d80 0x30>;
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interrupts = <3>;
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clock-names = "audio", "bitclk";
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clocks = <&soc_clocks MMP2_CLK_AUDIO>,
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<&audio_clk MMP2_CLK_AUDIO_SSPA1>;
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power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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};
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apb@d4000000 { /* APB */
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compatible = "mrvl,apb-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd4000000 0x00200000>;
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ranges;
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dma-controller@d4000000 {
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compatible = "marvell,pdma-1.0";
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reg = <0xd4000000 0x10000>;
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interrupts = <48>;
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/* For backwards compatibility: */
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#dma-channels = <16>;
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dma-channels = <16>;
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status = "disabled";
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};
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timer0: timer@d4014000 {
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compatible = "mrvl,mmp-timer";
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reg = <0xd4014000 0x100>;
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interrupts = <13>;
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clocks = <&soc_clocks MMP2_CLK_TIMER>;
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};
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uart1: serial@d4030000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0xd4030000 0x1000>;
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interrupts = <27>;
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clocks = <&soc_clocks MMP2_CLK_UART0>;
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resets = <&soc_clocks MMP2_CLK_UART0>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@d4017000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0xd4017000 0x1000>;
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interrupts = <28>;
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clocks = <&soc_clocks MMP2_CLK_UART1>;
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resets = <&soc_clocks MMP2_CLK_UART1>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart3: serial@d4018000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0xd4018000 0x1000>;
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interrupts = <24>;
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clocks = <&soc_clocks MMP2_CLK_UART2>;
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resets = <&soc_clocks MMP2_CLK_UART2>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart4: serial@d4016000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0xd4016000 0x1000>;
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interrupts = <46>;
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clocks = <&soc_clocks MMP2_CLK_UART3>;
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resets = <&soc_clocks MMP2_CLK_UART3>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio: gpio@d4019000 {
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compatible = "marvell,mmp2-gpio";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd4019000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <49>;
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interrupt-names = "gpio_mux";
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clocks = <&soc_clocks MMP2_CLK_GPIO>;
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resets = <&soc_clocks MMP2_CLK_GPIO>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges;
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gcb0: gpio@d4019000 {
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reg = <0xd4019000 0x4>;
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};
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gcb1: gpio@d4019004 {
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reg = <0xd4019004 0x4>;
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};
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gcb2: gpio@d4019008 {
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reg = <0xd4019008 0x4>;
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};
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gcb3: gpio@d4019100 {
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reg = <0xd4019100 0x4>;
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};
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gcb4: gpio@d4019104 {
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reg = <0xd4019104 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gcb5: gpio@d4019108 {
|
||
|
|
reg = <0xd4019108 0x4>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
twsi1: i2c@d4011000 {
|
||
|
|
compatible = "mrvl,mmp-twsi";
|
||
|
|
reg = <0xd4011000 0x1000>;
|
||
|
|
interrupts = <7>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_TWSI0>;
|
||
|
|
resets = <&soc_clocks MMP2_CLK_TWSI0>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
mrvl,i2c-fast-mode;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
twsi2: i2c@d4031000 {
|
||
|
|
compatible = "mrvl,mmp-twsi";
|
||
|
|
reg = <0xd4031000 0x1000>;
|
||
|
|
interrupt-parent = <&intcmux17>;
|
||
|
|
interrupts = <0>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_TWSI1>;
|
||
|
|
resets = <&soc_clocks MMP2_CLK_TWSI1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
twsi3: i2c@d4032000 {
|
||
|
|
compatible = "mrvl,mmp-twsi";
|
||
|
|
reg = <0xd4032000 0x1000>;
|
||
|
|
interrupt-parent = <&intcmux17>;
|
||
|
|
interrupts = <1>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_TWSI2>;
|
||
|
|
resets = <&soc_clocks MMP2_CLK_TWSI2>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
twsi4: i2c@d4033000 {
|
||
|
|
compatible = "mrvl,mmp-twsi";
|
||
|
|
reg = <0xd4033000 0x1000>;
|
||
|
|
interrupt-parent = <&intcmux17>;
|
||
|
|
interrupts = <2>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_TWSI3>;
|
||
|
|
resets = <&soc_clocks MMP2_CLK_TWSI3>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
twsi5: i2c@d4033800 {
|
||
|
|
compatible = "mrvl,mmp-twsi";
|
||
|
|
reg = <0xd4033800 0x1000>;
|
||
|
|
interrupt-parent = <&intcmux17>;
|
||
|
|
interrupts = <3>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_TWSI4>;
|
||
|
|
resets = <&soc_clocks MMP2_CLK_TWSI4>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
twsi6: i2c@d4034000 {
|
||
|
|
compatible = "mrvl,mmp-twsi";
|
||
|
|
reg = <0xd4034000 0x1000>;
|
||
|
|
interrupt-parent = <&intcmux17>;
|
||
|
|
interrupts = <4>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_TWSI5>;
|
||
|
|
resets = <&soc_clocks MMP2_CLK_TWSI5>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
rtc: rtc@d4010000 {
|
||
|
|
compatible = "mrvl,mmp-rtc";
|
||
|
|
reg = <0xd4010000 0x1000>;
|
||
|
|
interrupts = <1>, <0>;
|
||
|
|
interrupt-names = "rtc 1Hz", "rtc alarm";
|
||
|
|
interrupt-parent = <&intcmux5>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_RTC>;
|
||
|
|
resets = <&soc_clocks MMP2_CLK_RTC>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ssp1: spi@d4035000 {
|
||
|
|
compatible = "marvell,mmp2-ssp";
|
||
|
|
reg = <0xd4035000 0x1000>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_SSP0>;
|
||
|
|
interrupts = <0>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ssp2: spi@d4036000 {
|
||
|
|
compatible = "marvell,mmp2-ssp";
|
||
|
|
reg = <0xd4036000 0x1000>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_SSP1>;
|
||
|
|
interrupts = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ssp3: spi@d4037000 {
|
||
|
|
compatible = "marvell,mmp2-ssp";
|
||
|
|
reg = <0xd4037000 0x1000>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_SSP2>;
|
||
|
|
interrupts = <20>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ssp4: spi@d4039000 {
|
||
|
|
compatible = "marvell,mmp2-ssp";
|
||
|
|
reg = <0xd4039000 0x1000>;
|
||
|
|
clocks = <&soc_clocks MMP2_CLK_SSP3>;
|
||
|
|
interrupts = <21>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
asram: sram@e0000000 {
|
||
|
|
compatible = "mmio-sram";
|
||
|
|
reg = <0xe0000000 0x10000>;
|
||
|
|
ranges = <0 0xe0000000 0x10000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
soc_clocks: clocks {
|
||
|
|
compatible = "marvell,mmp2-clock";
|
||
|
|
reg = <0xd4050000 0x2000>,
|
||
|
|
<0xd4282800 0x400>,
|
||
|
|
<0xd4015000 0x1000>;
|
||
|
|
reg-names = "mpmu", "apmu", "apbc";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
#power-domain-cells = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|