97 lines
1.8 KiB
Plaintext
97 lines
1.8 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020 HiSilicon Limited.
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*
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* DTS file for Hisilicon SD5203 Board
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*/
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/dts-v1/;
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/ {
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model = "Hisilicon SD5203";
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compatible = "H836ASDJ", "hisilicon,sd5203";
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interrupt-parent = <&vic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
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};
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aliases {
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serial0 = &uart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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reg = <0x0>;
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};
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};
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memory@30000000 {
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device_type = "memory";
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reg = <0x30000000 0x8000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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vic: interrupt-controller@10130000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x10130000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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refclk125mhz: refclk125mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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timer0: timer@16002000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x16002000 0x1000>;
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interrupts = <4>;
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clocks = <&refclk125mhz>;
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clock-names = "apb_pclk";
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};
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timer1: timer@16003000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x16003000 0x1000>;
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interrupts = <5>;
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clocks = <&refclk125mhz>;
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clock-names = "apb_pclk";
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};
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uart0: serial@1600d000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x1600d000 0x1000>;
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bus_id = "uart0";
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clocks = <&refclk125mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <17>;
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};
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uart1: serial@1600c000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x1600c000 0x1000>;
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clocks = <&refclk125mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <16>;
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status = "disabled";
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};
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};
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};
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