82 lines
1.5 KiB
Plaintext
82 lines
1.5 KiB
Plaintext
|
// SPDX-License-Identifier: GPL-2.0
|
||
|
|
/*
|
||
|
|
* Copyright 2022 Google LLC
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include "socfpga_arria10.dtsi"
|
||
|
|
|
||
|
|
/ {
|
||
|
|
|
||
|
|
model = "Enclustra Mercury AA1";
|
||
|
|
compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
|
||
|
|
|
||
|
|
aliases {
|
||
|
|
ethernet0 = &gmac0;
|
||
|
|
serial1 = &uart1;
|
||
|
|
};
|
||
|
|
|
||
|
|
memory@0 {
|
||
|
|
name = "memory";
|
||
|
|
device_type = "memory";
|
||
|
|
reg = <0x0 0x80000000>; /* 2GB */
|
||
|
|
};
|
||
|
|
|
||
|
|
chosen {
|
||
|
|
stdout-path = "serial1:115200n8";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&gmac0 {
|
||
|
|
phy-mode = "rgmii";
|
||
|
|
phy-addr = <0xffffffff>; /* probe for phy addr */
|
||
|
|
|
||
|
|
max-frame-size = <3800>;
|
||
|
|
|
||
|
|
phy-handle = <&phy3>;
|
||
|
|
|
||
|
|
mdio {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "snps,dwmac-mdio";
|
||
|
|
phy3: ethernet-phy@3 {
|
||
|
|
txd0-skew-ps = <0>; /* -420ps */
|
||
|
|
txd1-skew-ps = <0>; /* -420ps */
|
||
|
|
txd2-skew-ps = <0>; /* -420ps */
|
||
|
|
txd3-skew-ps = <0>; /* -420ps */
|
||
|
|
rxd0-skew-ps = <420>; /* 0ps */
|
||
|
|
rxd1-skew-ps = <420>; /* 0ps */
|
||
|
|
rxd2-skew-ps = <420>; /* 0ps */
|
||
|
|
rxd3-skew-ps = <420>; /* 0ps */
|
||
|
|
txen-skew-ps = <0>; /* -420ps */
|
||
|
|
txc-skew-ps = <1860>; /* 960ps */
|
||
|
|
rxdv-skew-ps = <420>; /* 0ps */
|
||
|
|
rxc-skew-ps = <1680>; /* 780ps */
|
||
|
|
reg = <3>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c1 {
|
||
|
|
atsha204a: crypto@64 {
|
||
|
|
compatible = "atmel,atsha204a";
|
||
|
|
reg = <0x64>;
|
||
|
|
};
|
||
|
|
|
||
|
|
isl12022: isl12022@6f {
|
||
|
|
compatible = "isil,isl12022";
|
||
|
|
reg = <0x6f>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Following mappings are taken from arria10 socdk dts */
|
||
|
|
&mmc {
|
||
|
|
cap-sd-highspeed;
|
||
|
|
broken-cd;
|
||
|
|
bus-width = <4>;
|
||
|
|
clk-phase-sd-hs = <0>, <135>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&osc1 {
|
||
|
|
clock-frequency = <33330000>;
|
||
|
|
};
|