413 lines
11 KiB
C
413 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AM33XX CM functions
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Reference taken from from OMAP4 cminst44xx.c
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm.h"
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#include "cm33xx.h"
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#include "cm-regbits-34xx.h"
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#include "cm-regbits-33xx.h"
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#include "prm33xx.h"
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/*
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* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
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*
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* 0x0 func: Module is fully functional, including OCP
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* 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
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* abortion
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* 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
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* using separate functional clock
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* 0x3 disabled: Module is disabled and cannot be accessed
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*
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*/
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#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
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#define CLKCTRL_IDLEST_INTRANSITION 0x1
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#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
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#define CLKCTRL_IDLEST_DISABLED 0x3
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/* Private functions */
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/* Read a register in a CM instance */
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static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
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{
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return readl_relaxed(cm_base.va + inst + idx);
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}
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/* Write into a register in a CM */
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static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
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{
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writel_relaxed(val, cm_base.va + inst + idx);
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}
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/* Read-modify-write a register in CM */
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static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
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{
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u32 v;
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v = am33xx_cm_read_reg(inst, idx);
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v &= ~mask;
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v |= bits;
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am33xx_cm_write_reg(v, inst, idx);
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return v;
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}
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static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
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{
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u32 v;
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v = am33xx_cm_read_reg(inst, idx);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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/**
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* _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
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* bit 0.
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*/
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static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
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{
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u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
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v &= AM33XX_IDLEST_MASK;
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v >>= AM33XX_IDLEST_SHIFT;
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return v;
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}
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/**
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* _is_module_ready - can module registers be accessed without causing an abort?
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
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* *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
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*/
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static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
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{
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u32 v;
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v = _clkctrl_idlest(inst, clkctrl_offs);
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return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
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v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
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}
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/**
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* _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
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* @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* @c must be the unshifted value for CLKTRCTRL - i.e., this function
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* will handle the shift itself.
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*/
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static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
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{
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u32 v;
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v = am33xx_cm_read_reg(inst, cdoffs);
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v &= ~AM33XX_CLKTRCTRL_MASK;
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v |= c << AM33XX_CLKTRCTRL_SHIFT;
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am33xx_cm_write_reg(v, inst, cdoffs);
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}
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/* Public functions */
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/**
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* am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Returns true if the clockdomain referred to by (@inst, @cdoffs)
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* is in hardware-supervised idle mode, or 0 otherwise.
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*/
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static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
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{
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u32 v;
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v = am33xx_cm_read_reg(inst, cdoffs);
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v &= AM33XX_CLKTRCTRL_MASK;
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v >>= AM33XX_CLKTRCTRL_SHIFT;
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return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
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}
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/**
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* am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@inst, @cdoffs) into
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* hardware-supervised idle mode. No return value.
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*/
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static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
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}
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/**
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* am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@inst, @cdoffs) into
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* software-supervised idle mode, i.e., controlled manually by the
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* Linux OMAP clockdomain code. No return value.
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*/
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static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
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}
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/**
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* am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@inst, @cdoffs) into idle
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* No return value.
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*/
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static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
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}
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/**
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* am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
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* waking it up. No return value.
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*/
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static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
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}
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/*
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*
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*/
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/**
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* am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
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* @part: PRCM partition, ignored for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @bit_shift: bit shift for the register, ignored for AM33xx
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*
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* Wait for the module IDLEST to be functional. If the idle state is in any
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* the non functional state (trans, idle or disabled), module and thus the
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* sysconfig cannot be accessed and will probably lead to an "imprecise
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* external abort"
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*/
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static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
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u8 bit_shift)
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{
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int i = 0;
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omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
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MAX_MODULE_READY_TIME, i);
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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/**
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* am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
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* state
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* @part: CM partition, ignored for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @bit_shift: bit shift for the register, ignored for AM33xx
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*
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* Wait for the module IDLEST to be disabled. Some PRCM transition,
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* like reset assertion or parent clock de-activation must wait the
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* module to be fully disabled.
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*/
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static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
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u8 bit_shift)
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{
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int i = 0;
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omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
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CLKCTRL_IDLEST_DISABLED),
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MAX_MODULE_READY_TIME, i);
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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/**
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* am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
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* @mode: Module mode (SW or HW)
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* @part: CM partition, ignored for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* No return value.
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*/
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static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst,
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u16 clkctrl_offs)
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{
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u32 v;
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v = am33xx_cm_read_reg(inst, clkctrl_offs);
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v &= ~AM33XX_MODULEMODE_MASK;
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v |= mode << AM33XX_MODULEMODE_SHIFT;
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am33xx_cm_write_reg(v, inst, clkctrl_offs);
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}
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/**
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* am33xx_cm_module_disable - Disable the module inside CLKCTRL
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* @part: CM partition, ignored for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* No return value.
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*/
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static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
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{
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u32 v;
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v = am33xx_cm_read_reg(inst, clkctrl_offs);
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v &= ~AM33XX_MODULEMODE_MASK;
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am33xx_cm_write_reg(v, inst, clkctrl_offs);
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}
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/*
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* Clockdomain low-level functions
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*/
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static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
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return 0;
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}
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static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
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return 0;
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}
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static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
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}
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static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
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}
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static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
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{
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if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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return am33xx_clkdm_wakeup(clkdm);
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return 0;
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}
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static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
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if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
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am33xx_clkdm_sleep(clkdm);
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return 0;
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}
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static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset)
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{
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return cm_base.pa + inst + offset;
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}
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/**
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* am33xx_clkdm_save_context - Save the clockdomain transition context
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* @clkdm: The clockdomain pointer whose context needs to be saved
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*
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* Save the clockdomain transition context.
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*/
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static int am33xx_clkdm_save_context(struct clockdomain *clkdm)
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{
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clkdm->context = am33xx_cm_read_reg_bits(clkdm->cm_inst,
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clkdm->clkdm_offs,
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AM33XX_CLKTRCTRL_MASK);
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return 0;
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}
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/**
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* am33xx_restore_save_context - Restore the clockdomain transition context
|
||
|
|
* @clkdm: The clockdomain pointer whose context needs to be restored
|
||
|
|
*
|
||
|
|
* Restore the clockdomain transition context.
|
||
|
|
*/
|
||
|
|
static int am33xx_clkdm_restore_context(struct clockdomain *clkdm)
|
||
|
|
{
|
||
|
|
switch (clkdm->context) {
|
||
|
|
case OMAP34XX_CLKSTCTRL_DISABLE_AUTO:
|
||
|
|
am33xx_clkdm_deny_idle(clkdm);
|
||
|
|
break;
|
||
|
|
case OMAP34XX_CLKSTCTRL_FORCE_SLEEP:
|
||
|
|
am33xx_clkdm_sleep(clkdm);
|
||
|
|
break;
|
||
|
|
case OMAP34XX_CLKSTCTRL_FORCE_WAKEUP:
|
||
|
|
am33xx_clkdm_wakeup(clkdm);
|
||
|
|
break;
|
||
|
|
case OMAP34XX_CLKSTCTRL_ENABLE_AUTO:
|
||
|
|
am33xx_clkdm_allow_idle(clkdm);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct clkdm_ops am33xx_clkdm_operations = {
|
||
|
|
.clkdm_sleep = am33xx_clkdm_sleep,
|
||
|
|
.clkdm_wakeup = am33xx_clkdm_wakeup,
|
||
|
|
.clkdm_allow_idle = am33xx_clkdm_allow_idle,
|
||
|
|
.clkdm_deny_idle = am33xx_clkdm_deny_idle,
|
||
|
|
.clkdm_clk_enable = am33xx_clkdm_clk_enable,
|
||
|
|
.clkdm_clk_disable = am33xx_clkdm_clk_disable,
|
||
|
|
.clkdm_save_context = am33xx_clkdm_save_context,
|
||
|
|
.clkdm_restore_context = am33xx_clkdm_restore_context,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct cm_ll_data am33xx_cm_ll_data = {
|
||
|
|
.wait_module_ready = &am33xx_cm_wait_module_ready,
|
||
|
|
.wait_module_idle = &am33xx_cm_wait_module_idle,
|
||
|
|
.module_enable = &am33xx_cm_module_enable,
|
||
|
|
.module_disable = &am33xx_cm_module_disable,
|
||
|
|
.xlate_clkctrl = &am33xx_cm_xlate_clkctrl,
|
||
|
|
};
|
||
|
|
|
||
|
|
int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
|
||
|
|
{
|
||
|
|
return cm_register(&am33xx_cm_ll_data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit am33xx_cm_exit(void)
|
||
|
|
{
|
||
|
|
cm_unregister(&am33xx_cm_ll_data);
|
||
|
|
}
|
||
|
|
__exitcall(am33xx_cm_exit);
|