329 lines
8.6 KiB
C
329 lines
8.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP4 specific common source file.
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/platform_device.h>
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#include <linux/memblock.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/export.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of_address.h>
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#include <linux/reboot.h>
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#include <linux/genalloc.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include <asm/memblock.h>
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#include <asm/smp_twd.h>
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#include "omap-wakeupgen.h"
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#include "soc.h"
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#include "iomap.h"
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#include "common.h"
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#include "prminst44xx.h"
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#include "prcm_mpu44xx.h"
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#include "omap4-sar-layout.h"
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#include "omap-secure.h"
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#include "sram.h"
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#ifdef CONFIG_CACHE_L2X0
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static void __iomem *l2cache_base;
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#endif
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static void __iomem *sar_ram_base;
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static void __iomem *gic_dist_base_addr;
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static void __iomem *twd_base;
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#define IRQ_LOCALTIMER 29
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#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
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/* Used to implement memory barrier on DRAM path */
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#define OMAP4_DRAM_BARRIER_VA 0xfe600000
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static void __iomem *dram_sync, *sram_sync;
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static phys_addr_t dram_sync_paddr;
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static u32 dram_sync_size;
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/*
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* The OMAP4 bus structure contains asynchronous bridges which can buffer
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* data writes from the MPU. These asynchronous bridges can be found on
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* paths between the MPU to EMIF, and the MPU to L3 interconnects.
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*
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* We need to be careful about re-ordering which can happen as a result
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* of different accesses being performed via different paths, and
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* therefore different asynchronous bridges.
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*/
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/*
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* OMAP4 interconnect barrier which is called for each mb() and wmb().
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* This is to ensure that normal paths to DRAM (normal memory, cacheable
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* accesses) are properly synchronised with writes to DMA coherent memory
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* (normal memory, uncacheable) and device writes.
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*
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* The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
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* path, as we need to ensure that data is visible to other system
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* masters prior to writes to those system masters being seen.
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*
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* Note: the SRAM path is not synchronised via mb() and wmb().
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*/
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static void omap4_mb(void)
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{
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if (dram_sync)
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writel_relaxed(0, dram_sync);
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}
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/*
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* OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
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*
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* If a data is stalled inside asynchronous bridge because of back
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* pressure, it may be accepted multiple times, creating pointer
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* misalignment that will corrupt next transfers on that data path until
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* next reset of the system. No recovery procedure once the issue is hit,
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* the path remains consistently broken.
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*
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* Async bridges can be found on paths between MPU to EMIF and MPU to L3
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* interconnects.
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*
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* This situation can happen only when the idle is initiated by a Master
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* Request Disconnection (which is trigged by software when executing WFI
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* on the CPU).
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*
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* The work-around for this errata needs all the initiators connected
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* through an async bridge to ensure that data path is properly drained
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* before issuing WFI. This condition will be met if one Strongly ordered
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* access is performed to the target right before executing the WFI.
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*
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* In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
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* IO barrier ensure that there is no synchronisation loss on initiators
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* operating on both interconnect port simultaneously.
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*
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* This is a stronger version of the OMAP4 memory barrier below, and
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* operates on both the MPU->MA->EMIF path but also the MPU->OCP path
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* as well, and is necessary prior to executing a WFI.
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*/
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void omap_interconnect_sync(void)
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{
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if (dram_sync && sram_sync) {
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writel_relaxed(readl_relaxed(dram_sync), dram_sync);
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writel_relaxed(readl_relaxed(sram_sync), sram_sync);
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isb();
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}
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}
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static int __init omap4_sram_init(void)
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{
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struct device_node *np;
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struct gen_pool *sram_pool;
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if (!soc_is_omap44xx() && !soc_is_omap54xx())
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return 0;
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np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
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if (!np)
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pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
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__func__);
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sram_pool = of_gen_pool_get(np, "sram", 0);
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if (!sram_pool)
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pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
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__func__);
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else
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sram_sync = (void __iomem *)gen_pool_alloc(sram_pool, PAGE_SIZE);
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of_node_put(np);
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return 0;
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}
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omap_arch_initcall(omap4_sram_init);
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/* Steal one page physical memory for barrier implementation */
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void __init omap_barrier_reserve_memblock(void)
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{
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dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
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dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
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}
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void __init omap_barriers_init(void)
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{
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struct map_desc dram_io_desc[1];
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dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
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dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
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dram_io_desc[0].length = dram_sync_size;
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dram_io_desc[0].type = MT_MEMORY_RW_SO;
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iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
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dram_sync = (void __iomem *) dram_io_desc[0].virtual;
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pr_info("OMAP4: Map %pa to %p for dram barrier\n",
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&dram_sync_paddr, dram_sync);
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soc_mb = omap4_mb;
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}
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#endif
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void gic_dist_disable(void)
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{
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if (gic_dist_base_addr)
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writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
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}
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void gic_dist_enable(void)
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{
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if (gic_dist_base_addr)
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writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
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}
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bool gic_dist_disabled(void)
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{
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return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
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}
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void gic_timer_retrigger(void)
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{
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u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
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u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
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u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
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if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
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/*
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* The local timer interrupt got lost while the distributor was
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* disabled. Ack the pending interrupt, and retrigger it.
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*/
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pr_warn("%s: lost localtimer interrupt\n", __func__);
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writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
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if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
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writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
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twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
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writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
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}
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}
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}
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *omap4_get_l2cache_base(void)
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{
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return l2cache_base;
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}
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void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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unsigned smc_op;
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switch (reg) {
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case L2X0_CTRL:
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smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
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break;
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case L2X0_AUX_CTRL:
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smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
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break;
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case L2X0_DEBUG_CTRL:
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smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
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break;
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case L310_PREFETCH_CTRL:
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smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
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break;
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case L310_POWER_CTRL:
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pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
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return;
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default:
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WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
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return;
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}
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omap_smc1(smc_op, val);
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}
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int __init omap_l2_cache_init(void)
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{
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/* Static mapping, never released */
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l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
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if (WARN_ON(!l2cache_base))
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return -ENOMEM;
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return 0;
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}
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#endif
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void __iomem *omap4_get_sar_ram_base(void)
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{
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return sar_ram_base;
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}
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/*
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* SAR RAM used to save and restore the HW context in low power modes.
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* Note that we need to initialize this very early for kexec. See
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* omap4_mpuss_early_init().
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*/
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void __init omap4_sar_ram_init(void)
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{
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unsigned long sar_base;
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/*
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (cpu_is_omap44xx())
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sar_base = OMAP44XX_SAR_RAM_BASE;
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else if (soc_is_omap54xx())
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sar_base = OMAP54XX_SAR_RAM_BASE;
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else
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return;
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/* Static mapping, never released */
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sar_ram_base = ioremap(sar_base, SZ_16K);
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if (WARN_ON(!sar_ram_base))
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return;
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}
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static const struct of_device_id intc_match[] = {
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{ .compatible = "ti,omap4-wugen-mpu", },
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{ .compatible = "ti,omap5-wugen-mpu", },
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{ },
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};
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static struct device_node *intc_node;
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void __init omap_gic_of_init(void)
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{
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struct device_node *np;
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intc_node = of_find_matching_node(NULL, intc_match);
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if (WARN_ON(!intc_node)) {
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pr_err("No WUGEN found in DT, system will misbehave.\n");
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pr_err("UPDATE YOUR DEVICE TREE!\n");
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}
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/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
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if (!cpu_is_omap446x())
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goto skip_errata_init;
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
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gic_dist_base_addr = of_iomap(np, 0);
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of_node_put(np);
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WARN_ON(!gic_dist_base_addr);
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
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twd_base = of_iomap(np, 0);
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of_node_put(np);
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WARN_ON(!twd_base);
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skip_errata_init:
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irqchip_init();
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}
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