115 lines
4.4 KiB
C
115 lines
4.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* OMAP44xx PRM instance offset macros
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*
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* Copyright (C) 2009-2011 Texas Instruments, Inc.
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Paul Walmsley (paul@pwsan.com)
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* Rajendra Nayak (rnayak@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
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* or "OMAP4430".
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
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#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
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#include "prm44xx_54xx.h"
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#include "prm.h"
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#define OMAP4430_PRM_BASE 0x4a306000
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#define OMAP44XX_PRM_REGADDR(inst, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
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/* PRM instances */
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#define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
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#define OMAP4430_PRM_CKGEN_INST 0x0100
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#define OMAP4430_PRM_MPU_INST 0x0300
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#define OMAP4430_PRM_TESLA_INST 0x0400
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#define OMAP4430_PRM_ABE_INST 0x0500
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#define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
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#define OMAP4430_PRM_CORE_INST 0x0700
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#define OMAP4430_PRM_IVAHD_INST 0x0f00
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#define OMAP4430_PRM_CAM_INST 0x1000
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#define OMAP4430_PRM_DSS_INST 0x1100
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#define OMAP4430_PRM_GFX_INST 0x1200
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#define OMAP4430_PRM_L3INIT_INST 0x1300
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#define OMAP4430_PRM_L4PER_INST 0x1400
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#define OMAP4430_PRM_CEFUSE_INST 0x1600
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#define OMAP4430_PRM_WKUP_INST 0x1700
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#define OMAP4430_PRM_WKUP_CM_INST 0x1800
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#define OMAP4430_PRM_EMU_INST 0x1900
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#define OMAP4430_PRM_EMU_CM_INST 0x1a00
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#define OMAP4430_PRM_DEVICE_INST 0x1b00
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/* PRM clockdomain register offsets (from instance start) */
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#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
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#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
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/* OMAP4 specific register offsets */
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#define OMAP4_RM_RSTST 0x0004
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#define OMAP4_PM_PWSTCTRL 0x0000
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#define OMAP4_PM_PWSTST 0x0004
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/* PRM.OCP_SOCKET_PRM register offsets */
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#define OMAP4_REVISION_PRM_OFFSET 0x0000
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#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010
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#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
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#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
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#define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018
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#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
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/* PRM.MPU_PRM register offsets */
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#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
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/* PRM.DEVICE_PRM register offsets */
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#define OMAP4_PRM_RSTCTRL_OFFSET 0x0000
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#define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010
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#define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020
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#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
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#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
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#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030
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#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
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#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
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#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c
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#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040
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#define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044
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#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
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#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
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#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
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#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
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#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058
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#define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c
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#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
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#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
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#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
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#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
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#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070
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#define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074
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#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078
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#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c
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#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080
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#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084
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#define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088
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#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c
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#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090
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#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
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#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098
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#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c
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#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
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#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
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#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
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#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
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#endif
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