185 lines
6.4 KiB
C
185 lines
6.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/probes/kprobes/checkers-arm.c
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*
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* Copyright (C) 2014 Huawei Inc.
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*/
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#include <linux/kernel.h>
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#include "../decode.h"
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#include "../decode-arm.h"
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#include "checkers.h"
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static enum probes_insn __kprobes arm_check_stack(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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/*
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* PROBES_LDRSTRD, PROBES_LDMSTM, PROBES_STORE,
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* PROBES_STORE_EXTRA may get here. Simply mark all normal
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* insns as STACK_USE_NONE.
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*/
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static const union decode_item table[] = {
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/*
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* 'STR{,D,B,H}, Rt, [Rn, Rm]' should be marked as UNKNOWN
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* if Rn or Rm is SP.
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* x
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* STR (register) cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx
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* STRB (register) cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx
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*/
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DECODE_OR (0x0e10000f, 0x0600000d),
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DECODE_OR (0x0e1f0000, 0x060d0000),
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/*
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* x
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* STRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx
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* STRH (register) cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx
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*/
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DECODE_OR (0x0e5000bf, 0x000000bd),
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DECODE_CUSTOM (0x0e5f00b0, 0x000d00b0, STACK_USE_UNKNOWN),
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/*
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* For PROBES_LDMSTM, only stmdx sp, [...] need to examine
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*
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* Bit B/A (bit 24) encodes arithmetic operation order. 1 means
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* before, 0 means after.
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* Bit I/D (bit 23) encodes arithmetic operation. 1 means
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* increment, 0 means decrement.
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*
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* So:
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* B I
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* / /
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* A D | Rn |
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* STMDX SP, [...] cccc 100x 00x0 xxxx xxxx xxxx xxxx xxxx
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*/
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DECODE_CUSTOM (0x0edf0000, 0x080d0000, STACK_USE_STMDX),
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/* P U W | Rn | Rt | imm12 |*/
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/* STR (immediate) cccc 010x x0x0 1101 xxxx xxxx xxxx xxxx */
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/* STRB (immediate) cccc 010x x1x0 1101 xxxx xxxx xxxx xxxx */
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/* P U W | Rn | Rt |imm4| |imm4|*/
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/* STRD (immediate) cccc 000x x1x0 1101 xxxx xxxx 1111 xxxx */
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/* STRH (immediate) cccc 000x x1x0 1101 xxxx xxxx 1011 xxxx */
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/*
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* index = (P == '1'); add = (U == '1').
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* Above insns with:
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* index == 0 (str{,d,h} rx, [sp], #+/-imm) or
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* add == 1 (str{,d,h} rx, [sp, #+<imm>])
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* should be STACK_USE_NONE.
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* Only str{,b,d,h} rx,[sp,#-n] (P == 1 and U == 0) are
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* required to be examined.
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*/
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/* STR{,B} Rt,[SP,#-n] cccc 0101 0xx0 1101 xxxx xxxx xxxx xxxx */
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DECODE_CUSTOM (0x0f9f0000, 0x050d0000, STACK_USE_FIXED_XXX),
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/* STR{D,H} Rt,[SP,#-n] cccc 0001 01x0 1101 xxxx xxxx 1x11 xxxx */
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DECODE_CUSTOM (0x0fdf00b0, 0x014d00b0, STACK_USE_FIXED_X0X),
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/* fall through */
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DECODE_CUSTOM (0, 0, STACK_USE_NONE),
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DECODE_END
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};
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return probes_decode_insn(insn, asi, table, false, false, stack_check_actions, NULL);
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}
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const struct decode_checker arm_stack_checker[NUM_PROBES_ARM_ACTIONS] = {
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[PROBES_LDRSTRD] = {.checker = arm_check_stack},
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[PROBES_STORE_EXTRA] = {.checker = arm_check_stack},
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[PROBES_STORE] = {.checker = arm_check_stack},
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[PROBES_LDMSTM] = {.checker = arm_check_stack},
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};
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static enum probes_insn __kprobes arm_check_regs_nouse(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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asi->register_usage_flags = 0;
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return INSN_GOOD;
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}
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static enum probes_insn arm_check_regs_normal(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
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int i;
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asi->register_usage_flags = 0;
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for (i = 0; i < 5; regs >>= 4, insn >>= 4, i++)
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if (regs & 0xf)
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asi->register_usage_flags |= 1 << (insn & 0xf);
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return INSN_GOOD;
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}
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static enum probes_insn arm_check_regs_ldmstm(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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unsigned int reglist = insn & 0xffff;
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unsigned int rn = (insn >> 16) & 0xf;
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asi->register_usage_flags = reglist | (1 << rn);
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return INSN_GOOD;
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}
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static enum probes_insn arm_check_regs_mov_ip_sp(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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/* Instruction is 'mov ip, sp' i.e. 'mov r12, r13' */
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asi->register_usage_flags = (1 << 12) | (1<< 13);
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return INSN_GOOD;
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}
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/*
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* | Rn |Rt/d| | Rm |
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* LDRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx
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* STRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx
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* | Rn |Rt/d| |imm4L|
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* LDRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx
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* STRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx
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*
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* Such instructions access Rt/d and its next register, so different
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* from others, a specific checker is required to handle this extra
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* implicit register usage.
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*/
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static enum probes_insn arm_check_regs_ldrdstrd(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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int rdt = (insn >> 12) & 0xf;
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arm_check_regs_normal(insn, asi, h);
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asi->register_usage_flags |= 1 << (rdt + 1);
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return INSN_GOOD;
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}
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const struct decode_checker arm_regs_checker[NUM_PROBES_ARM_ACTIONS] = {
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[PROBES_MRS] = {.checker = arm_check_regs_normal},
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[PROBES_SATURATING_ARITHMETIC] = {.checker = arm_check_regs_normal},
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[PROBES_MUL1] = {.checker = arm_check_regs_normal},
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[PROBES_MUL2] = {.checker = arm_check_regs_normal},
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[PROBES_MUL_ADD_LONG] = {.checker = arm_check_regs_normal},
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[PROBES_MUL_ADD] = {.checker = arm_check_regs_normal},
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[PROBES_LOAD] = {.checker = arm_check_regs_normal},
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[PROBES_LOAD_EXTRA] = {.checker = arm_check_regs_normal},
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[PROBES_STORE] = {.checker = arm_check_regs_normal},
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[PROBES_STORE_EXTRA] = {.checker = arm_check_regs_normal},
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[PROBES_DATA_PROCESSING_REG] = {.checker = arm_check_regs_normal},
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[PROBES_DATA_PROCESSING_IMM] = {.checker = arm_check_regs_normal},
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[PROBES_SEV] = {.checker = arm_check_regs_nouse},
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[PROBES_WFE] = {.checker = arm_check_regs_nouse},
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[PROBES_SATURATE] = {.checker = arm_check_regs_normal},
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[PROBES_REV] = {.checker = arm_check_regs_normal},
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[PROBES_MMI] = {.checker = arm_check_regs_normal},
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[PROBES_PACK] = {.checker = arm_check_regs_normal},
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[PROBES_EXTEND] = {.checker = arm_check_regs_normal},
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[PROBES_EXTEND_ADD] = {.checker = arm_check_regs_normal},
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[PROBES_BITFIELD] = {.checker = arm_check_regs_normal},
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[PROBES_LDMSTM] = {.checker = arm_check_regs_ldmstm},
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[PROBES_MOV_IP_SP] = {.checker = arm_check_regs_mov_ip_sp},
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[PROBES_LDRSTRD] = {.checker = arm_check_regs_ldrdstrd},
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};
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