121 lines
3.0 KiB
Plaintext
121 lines
3.0 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020, 2022 NXP
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*/
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&flexspi0 {
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compatible = "nxp,imx8dxl-fspi";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio0 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 0 47 13>,
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<&iomuxc 13 61 4>,
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<&iomuxc 19 67 4>,
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<&iomuxc 24 72 1>;
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};
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&lsio_gpio1 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 4 74 5>,
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<&iomuxc 9 80 16>;
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};
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&lsio_gpio2 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 1 98 2>,
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<&iomuxc 3 101 1>,
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<&iomuxc 5 107 8>;
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};
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&lsio_gpio3 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 0 115 4>,
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<&iomuxc 9 121 1>,
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<&iomuxc 10 120 1>,
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<&iomuxc 11 123 1>,
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<&iomuxc 12 122 1>,
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<&iomuxc 13 125 1>,
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<&iomuxc 14 124 1>,
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<&iomuxc 16 126 1>,
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<&iomuxc 17 128 1>,
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<&iomuxc 18 131 1>,
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<&iomuxc 19 130 1>,
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<&iomuxc 20 133 1>,
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<&iomuxc 21 132 1>,
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<&iomuxc 22 129 1>,
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<&iomuxc 23 134 1>;
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};
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&lsio_gpio4 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 0 0 3>,
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<&iomuxc 3 4 4>,
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<&iomuxc 7 9 12>,
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<&iomuxc 19 22 2>,
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<&iomuxc 21 25 2>,
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<&iomuxc 29 29 3>;
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};
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&lsio_gpio5 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 0 32 3>,
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<&iomuxc 3 36 6>,
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<&iomuxc 9 43 3>;
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};
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&lsio_gpio6 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 0 53 7>,
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<&iomuxc 8 86 10>,
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<&iomuxc 19 107 8>;
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};
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&lsio_gpio7 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&iomuxc 0 0 3>,
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<&iomuxc 3 4 4>,
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<&iomuxc 8 22 2>,
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<&iomuxc 10 25 2>,
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<&iomuxc 16 44 2>;
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};
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&lsio_mu0 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu1 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu2 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu3 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu4 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu5 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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};
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