462 lines
11 KiB
Plaintext
462 lines
11 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2020 Compass Electronics Group, LLC
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*/
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/ {
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aliases {
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rtc0 = &rtc;
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rtc1 = &snvs_rtc;
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};
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usdhc1_pwrseq: usdhc1_pwrseq {
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1_gpio>;
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reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
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clocks = <&osc_32k>;
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clock-names = "ext_clock";
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post-power-on-delay-ms = <80>;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_1 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_2 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_3 {
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cpu-supply = <&buck2_reg>;
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25000000 {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-750000000 {
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opp-hz = /bits/ 64 <750000000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi>;
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status = "okay";
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flash@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <80000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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rohm,reset-snvs-powered;
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#clock-cells = <0>;
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clocks = <&osc_32k 0>;
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clock-output-names = "clk-32k-out";
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regulators {
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buck1_reg: BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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buck2_reg: BUCK2 {
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regulator-name = "buck2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <1000000>;
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rohm,dvs-idle-voltage = <900000>;
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};
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buck3_reg: BUCK3 {
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// BUCK5 in datasheet
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regulator-name = "buck3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck4_reg: BUCK4 {
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// BUCK6 in datasheet
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regulator-name = "buck4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5_reg: BUCK5 {
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// BUCK7 in datasheet
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regulator-name = "buck5";
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regulator-min-microvolt = <1605000>;
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regulator-max-microvolt = <1995000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6_reg: BUCK6 {
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// BUCK8 in datasheet
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regulator-name = "buck6";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: LDO1 {
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regulator-name = "ldo1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: LDO2 {
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regulator-name = "ldo2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: LDO3 {
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: LDO4 {
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regulator-name = "ldo4";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo6_reg: LDO6 {
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regulator-name = "ldo6";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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eeprom@50 {
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compatible = "microchip,24c64", "atmel,24c64";
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pagesize = <32>;
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read-only; /* Manufacturing EEPROM programmed at factory */
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reg = <0x50>;
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};
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rtc: rtc@51 {
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compatible = "nxp,pcf85263";
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reg = <0x51>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MM_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
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host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
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clocks = <&osc_32k>;
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max-speed = <4000000>;
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clock-names = "extclk";
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};
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};
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&usdhc1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <4>;
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non-removable;
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cap-power-off-card;
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keep-power-in-suspend;
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mmc-pwrseq = <&usdhc1_pwrseq>;
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status = "okay";
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brcmf: bcrmf@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wlan>;
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interrupt-parent = <&gpio2>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "host-wake";
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};
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
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MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
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>;
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};
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pinctrl_flexspi: flexspigrp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
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MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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>;
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};
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pinctrl_pmic: pmicirqgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
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MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
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MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
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MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
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MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
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MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||
|
|
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||
|
|
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||
|
|
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wlan: wlangrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|