443 lines
10 KiB
Plaintext
443 lines
10 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 Gateworks Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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/ {
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aliases {
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ethernet1 = ð1;
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usb0 = &usbotg1;
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usb1 = &usbotg2;
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};
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led-controller {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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pps {
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compatible = "pps-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pps>;
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gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "1P8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_usb_otg1_vbus: regulator-usb-otg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb1_en>;
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_usb_otg2_vbus: regulator-usb-otg2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb2_en>;
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compatible = "regulator-fixed";
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regulator-name = "usb_otg2_vbus";
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gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_wifi_en: regulator-wifi-en {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_wl>;
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compatible = "regulator-fixed";
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regulator-name = "wl";
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <100>;
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enable-active-high;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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/* off-board header */
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&gpio1 {
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gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
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"", "", "pci_usb_sel", "dio0",
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"", "dio1", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio4 {
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gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
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"mipi_gpio1", "", "", "pci_wdis#",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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accelerometer@19 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_accel>;
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compatible = "st,lis2de12";
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reg = <0x19>;
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st,drdy-int-pin = <1>;
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interrupt-parent = <&gpio4>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "INT1";
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};
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};
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/* off-board header */
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&pcie_phy {
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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fsl,clkreq-unsupported;
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clocks = <&pcie0_refclk>;
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clock-names = "ref";
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status = "okay";
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
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<&clk IMX8MM_CLK_PCIE1_AUX>;
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assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
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<&clk IMX8MM_CLK_PCIE1_CTRL>;
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assigned-clock-rates = <10000000>, <250000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
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<&clk IMX8MM_SYS_PLL2_250M>;
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status = "okay";
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pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie@1,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie@2,4 {
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reg = <0x2000 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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eth1: pcie@6,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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local-mac-address = [00 00 00 00 00 00];
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};
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};
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};
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};
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};
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/* off-board header */
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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/* GPS */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* bluetooth HCI */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
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cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
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rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm4330-bt";
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shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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};
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/* RS232 */
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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over-current-active-low;
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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vbus-supply = <®_usb_otg2_vbus>;
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status = "okay";
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};
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/* SDIO WiFi */
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <4>;
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non-removable;
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vmmc-supply = <®_wifi_en>;
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status = "okay";
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};
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/* microSD */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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vmmc-supply = <®_3p3v>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
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MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
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MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
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MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
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MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
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MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
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MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
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>;
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};
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pinctrl_accel: accelgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
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>;
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};
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pinctrl_bten: btengrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
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>;
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};
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pinctrl_gpio_leds: gpioledgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
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MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
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MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
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>;
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};
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pinctrl_pps: ppsgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
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>;
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};
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pinctrl_reg_wl: regwlgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
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>;
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};
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pinctrl_reg_usb1_en: regusb1grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
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MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
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>;
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};
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pinctrl_reg_usb2_en: regusb2grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
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>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
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MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
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MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
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MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
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MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
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>;
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};
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pinctrl_spi2: spi2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
|
||
|
|
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
|
||
|
|
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
|
||
|
|
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart1: uart1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||
|
|
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart3: uart3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
|
||
|
|
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
|
||
|
|
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
|
||
|
|
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart4: uart4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
|
||
|
|
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||
|
|
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
|
||
|
|
MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
|
||
|
|
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|