417 lines
9.9 KiB
Plaintext
417 lines
9.9 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
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*/
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/ {
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aliases {
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rtc0 = &rtc;
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rtc1 = &snvs_rtc;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0xc0000000>,
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<0x1 0x00000000 0 0xc0000000>;
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};
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reg_wl_bt: regulator-wifi-bt {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_wl_bt>;
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regulator-name = "wl-bt-pow-dwn";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
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startup-delay-us = <70000>;
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regulator-always-on;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2>;
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};
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&A53_1 {
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cpu-supply = <&buck2>;
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};
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&A53_2 {
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cpu-supply = <&buck2>;
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};
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&A53_3 {
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cpu-supply = <&buck2>;
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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snps,force_thresh_dma_mode;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@3 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <3>;
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reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio1>;
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interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi0>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <80000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <384000>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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buck1: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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};
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buck4: BUCK4 {
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regulator-name = "BUCK4";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5 {
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regulator-name = "BUCK5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3: LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-name = "LDO4";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <384000>;
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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pagesize = <32>;
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read-only; /* Manufacturing EEPROM programmed at factory */
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};
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rtc: rtc@51 {
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compatible = "nxp,pcf85263";
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reg = <0x51>;
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MP_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <4>;
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vmmc-supply = <®_wl_bt>;
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cap-sd-highspeed;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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keep-power-in-suspend;
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wakeup-source;
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non-removable;
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cap-power-off-card;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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mwifiex: wifi@1 {
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compatible = "marvell,sd8997";
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reg = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wlan>;
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interrupt-parent = <&gpio2>;
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interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
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MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
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MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
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>;
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};
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pinctrl_flexspi0: flexspi0grp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
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MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
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MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
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MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
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MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
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MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
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MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
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MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
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>;
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};
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pinctrl_pmic: pmicgrp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
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>;
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};
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pinctrl_reg_wl_bt: reg-wl-btgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
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MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
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MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
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MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
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MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
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MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
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MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
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MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
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MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
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MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
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MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
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MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
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MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
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MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
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MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wlan: wlangrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|