323 lines
7.4 KiB
Plaintext
323 lines
7.4 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree For AC5.
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*
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* Copyright (C) 2021 Marvell
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* Copyright (C) 2022 Allied Telesis Labs
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Marvell AC5 SoC";
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compatible = "marvell,ac5";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges;
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internal-regs@7f000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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/* 16M internal register @ 0x7f00_0000 */
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ranges = <0x0 0x0 0x7f000000 0x1000000>;
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dma-coherent;
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uart0: serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "okay";
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};
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uart1: serial@12100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "disabled";
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};
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uart2: serial@12200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12200 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12300 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "disabled";
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};
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mdio: mdio@22004 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x22004 0x4>;
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clocks = <&cnm_clock>;
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};
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i2c0: i2c@11000{
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compatible = "marvell,mv78230-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cnm_clock>;
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clock-names = "core";
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency=<100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-1 = <&i2c0_gpio>;
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scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "disabled";
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};
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i2c1: i2c@11100{
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compatible = "marvell,mv78230-i2c";
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cnm_clock>;
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clock-names = "core";
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency=<100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-1 = <&i2c1_gpio>;
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scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "disabled";
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl0 0 0 32>;
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marvell,pwm-offset = <0x1f0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio1: gpio@18140 {
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reg = <0x18140 0x40>;
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compatible = "marvell,orion-gpio";
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ngpios = <14>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl0 0 32 14>;
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marvell,pwm-offset = <0x1f0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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/*
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* Dedicated section for devices behind 32bit controllers so we
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* can configure specific DMA mapping for them
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*/
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behind-32bit-controller@7f000000 {
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compatible = "simple-bus";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
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/* Host phy ram starts at 0x200M */
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dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
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dma-coherent;
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eth0: ethernet@20000 {
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compatible = "marvell,armada-ac5-neta";
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reg = <0x0 0x20000 0x0 0x4000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cnm_clock>;
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phy-mode = "sgmii";
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status = "disabled";
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};
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eth1: ethernet@24000 {
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compatible = "marvell,armada-ac5-neta";
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reg = <0x0 0x24000 0x0 0x4000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cnm_clock>;
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phy-mode = "sgmii";
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status = "disabled";
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};
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usb0: usb@80000 {
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compatible = "marvell,orion-ehci";
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reg = <0x0 0x80000 0x0 0x500>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usb1: usb@a0000 {
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compatible = "marvell,orion-ehci";
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reg = <0x0 0xa0000 0x0 0x500>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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pinctrl0: pinctrl@80020100 {
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compatible = "marvell,ac5-pinctrl";
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reg = <0 0x80020100 0 0x20>;
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i2c0_pins: i2c0-pins {
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c0";
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};
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i2c0_gpio: i2c0-gpio-pins {
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "gpio";
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};
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i2c1_pins: i2c1-pins {
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marvell,pins = "mpp20", "mpp21";
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marvell,function = "i2c1";
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};
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i2c1_gpio: i2c1-gpio-pins {
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marvell,pins = "mpp20", "mpp21";
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marvell,function = "i2c1";
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};
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};
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spi0: spi@805a0000 {
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compatible = "marvell,armada-3700-spi";
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reg = <0x0 0x805a0000 0x0 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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clocks = <&spi_clock>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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status = "disabled";
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};
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spi1: spi@805a8000 {
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compatible = "marvell,armada-3700-spi";
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reg = <0x0 0x805a8000 0x0 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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clocks = <&spi_clock>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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status = "disabled";
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};
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gic: interrupt-controller@80600000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
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<0x0 0x80660000 0x0 0x40000>; /* GICR */
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interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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clocks {
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cnm_clock: cnm-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <328000000>;
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};
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spi_clock: spi-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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};
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