80 lines
1.5 KiB
Plaintext
80 lines
1.5 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*/
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/dts-v1/;
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#include "sparx5_pcb_common.dtsi"
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/ {
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model = "Sparx5 PCB125 Reference Board";
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compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x10000000>;
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};
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};
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&gpio {
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emmc_pins: emmc-pins {
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/* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
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* (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
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*/
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pins = "GPIO_34", "GPIO_38", "GPIO_39",
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"GPIO_40", "GPIO_41", "GPIO_42",
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"GPIO_43", "GPIO_44", "GPIO_45",
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"GPIO_46", "GPIO_47";
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drive-strength = <3>;
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function = "emmc";
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};
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};
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&sdhci0 {
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status = "okay";
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bus-width = <8>;
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non-removable;
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pinctrl-0 = <&emmc_pins>;
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max-frequency = <8000000>;
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microchip,clock-delay = <10>;
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};
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&spi0 {
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status = "okay";
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spi@0 {
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compatible = "spi-mux";
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mux-controls = <&mux>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>; /* CS0 */
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flash@9 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <8000000>;
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reg = <0x9>; /* SPI */
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};
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};
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spi@1 {
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compatible = "spi-mux";
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mux-controls = <&mux 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>; /* CS1 */
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flash@9 {
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compatible = "spi-nand";
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pinctrl-0 = <&cs1_pins>;
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pinctrl-names = "default";
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spi-max-frequency = <8000000>;
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reg = <0x9>; /* SPI */
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};
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};
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};
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&sgpio0 {
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status = "okay";
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microchip,sgpio-port-ranges = <0 23>;
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};
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&i2c1 {
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status = "okay";
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};
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