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linux-zen-server/arch/arm64/boot/dts/qcom/sm6115.dtsi

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Initial commit
2023-08-30 17:53:23 +02:00
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
*/
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x1>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x101>;
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
enable-method = "psci";
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x102>;
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
enable-method = "psci";
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x103>;
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
enable-method = "psci";
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm6115", "qcom,scm";
#reset-cells = <1>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: memory@45700000 {
reg = <0x0 0x45700000 0x0 0x600000>;
no-map;
};
xbl_aop_mem: memory@45e00000 {
reg = <0x0 0x45e00000 0x0 0x140000>;
no-map;
};
sec_apps_mem: memory@45fff000 {
reg = <0x0 0x45fff000 0x0 0x1000>;
no-map;
};
smem_mem: memory@46000000 {
compatible = "qcom,smem";
reg = <0x0 0x46000000 0x0 0x200000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
};
cdsp_sec_mem: memory@46200000 {
reg = <0x0 0x46200000 0x0 0x1e00000>;
no-map;
};
pil_modem_mem: memory@4ab00000 {
reg = <0x0 0x4ab00000 0x0 0x6900000>;
no-map;
};
pil_video_mem: memory@51400000 {
reg = <0x0 0x51400000 0x0 0x500000>;
no-map;
};
wlan_msa_mem: memory@51900000 {
reg = <0x0 0x51900000 0x0 0x100000>;
no-map;
};
pil_cdsp_mem: memory@51a00000 {
reg = <0x0 0x51a00000 0x0 0x1e00000>;
no-map;
};
pil_adsp_mem: memory@53800000 {
reg = <0x0 0x53800000 0x0 0x2800000>;
no-map;
};
pil_ipa_fw_mem: memory@56100000 {
reg = <0x0 0x56100000 0x0 0x10000>;
no-map;
};
pil_ipa_gsi_mem: memory@56110000 {
reg = <0x0 0x56110000 0x0 0x5000>;
no-map;
};
pil_gpu_mem: memory@56115000 {
reg = <0x0 0x56115000 0x0 0x2000>;
no-map;
};
cont_splash_memory: memory@5c000000 {
reg = <0x0 0x5c000000 0x0 0x00f00000>;
no-map;
};
dfps_data_memory: memory@5cf00000 {
reg = <0x0 0x5cf00000 0x0 0x0100000>;
no-map;
};
removed_mem: memory@60000000 {
reg = <0x0 0x60000000 0x0 0x3900000>;
no-map;
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-sm6115";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,sm6115-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_min_svs: opp1 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp2 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp4 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp5 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp7 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
};
};
};
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 30>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-mpss {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
tcsr_mutex: hwlock@340000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x00340000 0x0 0x20000>;
#hwlock-cells = <1>;
};
tlmm: pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x0 0x00500000 0x0 0x400000>,
<0x0 0x00900000 0x0 0x400000>,
<0x0 0x00d00000 0x0 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
qup_i2c0_default: qup-i2c0-default-state {
pins = "gpio0", "gpio1";
function = "qup0";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c1_default: qup-i2c1-default-state {
pins = "gpio4", "gpio5";
function = "qup1";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c2_default: qup-i2c2-default-state {
pins = "gpio6", "gpio7";
function = "qup2";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c3_default: qup-i2c3-default-state {
pins = "gpio8", "gpio9";
function = "qup3";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c4_default: qup-i2c4-default-state {
pins = "gpio12", "gpio13";
function = "qup4";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c5_default: qup-i2c5-default-state {
pins = "gpio14", "gpio15";
function = "qup5";
drive-strength = <2>;
bias-pull-up;
};
qup_spi0_default: qup-spi0-default-state {
pins = "gpio0", "gpio1","gpio2", "gpio3";
function = "qup0";
drive-strength = <2>;
bias-pull-up;
};
qup_spi1_default: qup-spi1-default-state {
pins = "gpio4", "gpio5", "gpio69", "gpio70";
function = "qup1";
drive-strength = <2>;
bias-pull-up;
};
qup_spi2_default: qup-spi2-default-state {
pins = "gpio6", "gpio7", "gpio71", "gpio80";
function = "qup2";
drive-strength = <2>;
bias-pull-up;
};
qup_spi3_default: qup-spi3-default-state {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "qup3";
drive-strength = <2>;
bias-pull-up;
};
qup_spi4_default: qup-spi4-default-state {
pins = "gpio12", "gpio13", "gpio96", "gpio97";
function = "qup4";
drive-strength = <2>;
bias-pull-up;
};
qup_spi5_default: qup-spi5-default-state {
pins = "gpio14", "gpio15", "gpio16", "gpio17";
function = "qup5";
drive-strength = <2>;
bias-pull-up;
};
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_state_off: sdc1-off-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc2_state_on: sdc2-on-state {
clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd-pins {
pins = "gpio88";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_state_off: sdc2-off-state {
clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
sd-cd-pins {
pins = "gpio88";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
};
};
gcc: clock-controller@1400000 {
compatible = "qcom,gcc-sm6115";
reg = <0x0 0x01400000 0x0 0x1f0000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
usb_1_hsphy: phy@1613000 {
compatible = "qcom,sm6115-qusb2-phy";
reg = <0x0 0x01613000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2_hstx_trim>;
status = "disabled";
};
qfprom@1b40000 {
compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
reg = <0x0 0x01b40000 0x0 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
qusb2_hstx_trim: hstx-trim@25b {
reg = <0x25b 0x1>;
bits = <1 4>;
};
};
rng: rng@1b53000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x01b53000 0x0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
spmi_bus: spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x01c40000 0x0 0x1100>,
<0x0 0x01e00000 0x0 0x2000000>,
<0x0 0x03e00000 0x0 0x100000>,
<0x0 0x03f00000 0x0 0xa0000>,
<0x0 0x01c0a000 0x0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
tsens0: thermal-sensor@4410000 {
compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
<0x0 0x04410000 0x0 0x8>; /* SROT */
#qcom,sensors = <16>;
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x0 0x045f0000 0x0 0x7000>;
};
sram@4690000 {
compatible = "qcom,rpm-stats";
reg = <0x0 0x04690000 0x0 0x10000>;
};
sdhc_1: mmc@4744000 {
compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x04744000 0x0 0x1000>,
<0x0 0x04745000 0x0 0x1000>,
<0x0 0x04748000 0x0 0x8000>;
reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface", "core", "xo", "ice";
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";
bus-width = <8>;
status = "disabled";
};
sdhc_2: mmc@4784000 {
compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x04784000 0x0 0x1000>;
reg-names = "hc";
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
pinctrl-0 = <&sdc2_state_on>;
pinctrl-1 = <&sdc2_state_off>;
pinctrl-names = "default", "sleep";
power-domains = <&rpmpd SM6115_VDDCX>;
operating-points-v2 = <&sdhc2_opp_table>;
iommus = <&apps_smmu 0x00a0 0x0>;
resets = <&gcc GCC_SDCC2_BCR>;
bus-width = <4>;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
status = "disabled";
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmpd_opp_nom>;
};
};
};
ufs_mem_hc: ufs@4804000 {
compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <1>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
iommus = <&apps_smmu 0x100 0>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"ice_core_clk";
freq-table-hz = <50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<0 0>,
<0 0>,
<0 0>,
<75000000 300000000>;
status = "disabled";
};
ufs_mem_phy: phy@4807000 {
compatible = "qcom,sm6115-qmp-ufs-phy";
reg = <0x0 0x04807000 0x0 0x1c4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: phy@4807400 {
reg = <0x0 0x04807400 0x0 0x098>,
<0x0 0x04807600 0x0 0x130>,
<0x0 0x04807c00 0x0 0x16c>;
#phy-cells = <0>;
};
};
gpi_dma0: dma-controller@4a00000 {
compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x04a00000 0x0 0x60000>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <10>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0xf6 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_0: geniqup@4ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x04ac0000 0x0 0x2000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
iommus = <&apps_smmu 0xe3 0x0>;
ranges;
status = "disabled";
i2c0: i2c@4a80000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a80000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@4a80000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x04a80000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@4a84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a84000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c1_default>;
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@4a84000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x04a84000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@4a88000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a88000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@4a88000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x04a88000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi2_default>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@4a8c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a8c000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c3_default>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@4a8c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x04a8c000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi3_default>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@4a90000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c4_default>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@4a90000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x04a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_default>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart4: serial@4a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x04a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c5: i2c@4a94000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a94000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c5_default>;
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@4a94000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x04a94000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi5_default>;
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
usb_1: usb@4ef8800 {
compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
reg = <0x0 0x04ef8800 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
qcom,select-utmi-as-pipe-clk;
status = "disabled";
usb_1_dwc3: usb@4e00000 {
compatible = "snps,dwc3";
reg = <0x0 0x04e00000 0x0 0xcd00>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb_1_hsphy>;
phy-names = "usb2-phy";
iommus = <&apps_smmu 0x120 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "high-speed";
dr_mode = "peripheral";
};
};
mdss: display-subsystem@5e00000 {
compatible = "qcom,sm6115-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdp: display-controller@5e01000 {
compatible = "qcom,sm6115-dpu";
reg = <0x0 0x05e01000 0x0 0x8f000>,
<0x0 0x05eb0000 0x0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"iface",
"core",
"lut",
"rot",
"vsync";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd SM6115_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmpd_opp_min_svs>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-256000000 {
opp-hz = /bits/ 64 <256000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmpd_opp_nom>;
};
};
};
mdss_dsi0: dsi@5e94000 {
compatible = "qcom,dsi-ctrl-6g-qcm2290";
reg = <0x0 0x05e94000 0x0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd SM6115_VDDCX>;
phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmpd_opp_min_svs>;
};
opp-164000000 {
opp-hz = /bits/ 64 <164000000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmpd_opp_svs>;
};
};
};
mdss_dsi0_phy: phy@5e94400 {
compatible = "qcom,dsi-phy-14nm-2290";
reg = <0x0 0x05e94400 0x0 0x100>,
<0x0 0x05e94500 0x0 0x300>,
<0x0 0x05e94800 0x0 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
};
dispcc: clock-controller@5f00000 {
compatible = "qcom,sm6115-dispcc";
reg = <0x0 0x05f00000 0 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
stm@8002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x08002000 0x0 0x1000>,
<0x0 0x0e280000 0x0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
stm_out: endpoint {
remote-endpoint = <&funnel_in0_in>;
};
};
};
};
cti0: cti@8010000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08010000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti1: cti@8011000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08011000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti2: cti@8012000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08012000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti3: cti@8013000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08013000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti4: cti@8014000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08014000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti5: cti@8015000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08015000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti6: cti@8016000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08016000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti7: cti@8017000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08017000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti8: cti@8018000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08018000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti9: cti@8019000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x08019000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti10: cti@801a000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0801a000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti11: cti@801b000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0801b000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti12: cti@801c000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0801c000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti13: cti@801d000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0801d000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti14: cti@801e000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0801e000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
cti15: cti@801f000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0801f000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
replicator@8046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x08046000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
replicator_out: endpoint {
remote-endpoint = <&etr_in>;
};
};
};
in-ports {
port {
replicator_in: endpoint {
remote-endpoint = <&etf_out>;
};
};
};
};
etf@8047000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x08047000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
port {
etf_in: endpoint {
remote-endpoint = <&merge_funnel_out>;
};
};
};
out-ports {
port {
etf_out: endpoint {
remote-endpoint = <&replicator_in>;
};
};
};
};
etr@8048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x08048000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
port {
etr_in: endpoint {
remote-endpoint = <&replicator_out>;
};
};
};
};
funnel@8041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x08041000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
funnel_in0_out: endpoint {
remote-endpoint = <&merge_funnel_in0>;
};
};
};
in-ports {
port {
funnel_in0_in: endpoint {
remote-endpoint = <&stm_out>;
};
};
};
};
funnel@8042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x08042000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
funnel_in1_out: endpoint {
remote-endpoint = <&merge_funnel_in1>;
};
};
};
in-ports {
port {
funnel_in1_in: endpoint {
remote-endpoint = <&funnel_apss1_out>;
};
};
};
};
funnel@8045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x08045000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint = <&etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint = <&funnel_in0_out>;
};
};
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint = <&funnel_in1_out>;
};
};
};
};
etm@9040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09040000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU0>;
status = "disabled";
out-ports {
port {
etm0_out: endpoint {
remote-endpoint = <&funnel_apss0_in0>;
};
};
};
};
etm@9140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09140000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU1>;
status = "disabled";
out-ports {
port {
etm1_out: endpoint {
remote-endpoint = <&funnel_apss0_in1>;
};
};
};
};
etm@9240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09240000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU2>;
status = "disabled";
out-ports {
port {
etm2_out: endpoint {
remote-endpoint = <&funnel_apss0_in2>;
};
};
};
};
etm@9340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09340000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU3>;
status = "disabled";
out-ports {
port {
etm3_out: endpoint {
remote-endpoint = <&funnel_apss0_in3>;
};
};
};
};
etm@9440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09440000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU4>;
status = "disabled";
out-ports {
port {
etm4_out: endpoint {
remote-endpoint = <&funnel_apss0_in4>;
};
};
};
};
etm@9540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09540000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU5>;
status = "disabled";
out-ports {
port {
etm5_out: endpoint {
remote-endpoint = <&funnel_apss0_in5>;
};
};
};
};
etm@9640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09640000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU6>;
status = "disabled";
out-ports {
port {
etm6_out: endpoint {
remote-endpoint = <&funnel_apss0_in6>;
};
};
};
};
etm@9740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x09740000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU7>;
status = "disabled";
out-ports {
port {
etm7_out: endpoint {
remote-endpoint = <&funnel_apss0_in7>;
};
};
};
};
funnel@9800000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x09800000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
funnel_apss0_out: endpoint {
remote-endpoint = <&funnel_apss1_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_apss0_in0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel_apss0_in1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
funnel_apss0_in2: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@3 {
reg = <3>;
funnel_apss0_in3: endpoint {
remote-endpoint = <&etm3_out>;
};
};
port@4 {
reg = <4>;
funnel_apss0_in4: endpoint {
remote-endpoint = <&etm4_out>;
};
};
port@5 {
reg = <5>;
funnel_apss0_in5: endpoint {
remote-endpoint = <&etm5_out>;
};
};
port@6 {
reg = <6>;
funnel_apss0_in6: endpoint {
remote-endpoint = <&etm6_out>;
};
};
port@7 {
reg = <7>;
funnel_apss0_in7: endpoint {
remote-endpoint = <&etm7_out>;
};
};
};
};
funnel@9810000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x09810000 0x0 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
funnel_apss1_out: endpoint {
remote-endpoint = <&funnel_in1_in>;
};
};
};
in-ports {
port {
funnel_apss1_in: endpoint {
remote-endpoint = <&funnel_apss0_out>;
};
};
};
};
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x0c600000 0x0 0x80000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
};
wifi: wifi@c800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0x0 0x0c800000 0x0 0x800000>;
reg-names = "membase";
memory-region = <&wlan_msa_mem>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x1a0 0x1>;
qcom,msa-fixed-perm;
status = "disabled";
};
watchdog@f017000 {
compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
reg = <0x0 0x0f017000 0x0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
};
apcs_glb: mailbox@f111000 {
compatible = "qcom,sm6115-apcs-hmss-global";
reg = <0x0 0x0f111000 0x0 0x1000>;
#mbox-cells = <1>;
};
timer@f120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0f120000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-frequency = <19200000>;
frame@f121000 {
reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>;
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
frame@f123000 {
reg = <0x0 0x0f123000 0x0 0x1000>;
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f124000 {
reg = <0x0 0x0f124000 0x0 0x1000>;
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f125000 {
reg = <0x0 0x0f125000 0x0 0x1000>;
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f126000 {
reg = <0x0 0x0f126000 0x0 0x1000>;
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f127000 {
reg = <0x0 0x0f127000 0x0 0x1000>;
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f128000 {
reg = <0x0 0x0f128000 0x0 0x1000>;
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0x0 0x0f200000 0x0 0x10000>,
<0x0 0x0f300000 0x0 0x100000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
cpufreq_hw: cpufreq@f521000 {
compatible = "qcom,cpufreq-hw";
reg = <0x0 0x0f521000 0x0 0x1000>,
<0x0 0x0f523000 0x0 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
};
thermal-zones {
mapss-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
cdsp-hvx-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
wlan-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
camera-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
video-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
cpu4-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
cpu4_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu5-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
cpu5_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu6-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
cpu6_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu7-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
cpu7_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu45-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
cpu45_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu45_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu45_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu67-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
cpu67_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu67_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu67_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0123-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
cpu0123_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu0123_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0123_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
modem0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
display-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
gpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};