628 lines
15 KiB
C
628 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 ARM Limited
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/perf_event.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/sysctl.h>
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#include <linux/uaccess.h>
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#include <asm/cpufeature.h>
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#include <asm/insn.h>
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#include <asm/sysreg.h>
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#include <asm/system_misc.h>
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#include <asm/traps.h>
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#define CREATE_TRACE_POINTS
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#include "trace-events-emulation.h"
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/*
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* The runtime support for deprecated instruction support can be in one of
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* following three states -
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*
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* 0 = undef
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* 1 = emulate (software emulation)
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* 2 = hw (supported in hardware)
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*/
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enum insn_emulation_mode {
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INSN_UNDEF,
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INSN_EMULATE,
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INSN_HW,
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};
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enum legacy_insn_status {
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INSN_DEPRECATED,
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INSN_OBSOLETE,
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INSN_UNAVAILABLE,
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};
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struct insn_emulation {
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const char *name;
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enum legacy_insn_status status;
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bool (*try_emulate)(struct pt_regs *regs,
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u32 insn);
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int (*set_hw_mode)(bool enable);
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int current_mode;
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int min;
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int max;
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/*
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* sysctl for this emulation + a sentinal entry.
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*/
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struct ctl_table sysctl[2];
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};
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#define ARM_OPCODE_CONDTEST_FAIL 0
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#define ARM_OPCODE_CONDTEST_PASS 1
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#define ARM_OPCODE_CONDTEST_UNCOND 2
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#define ARM_OPCODE_CONDITION_UNCOND 0xf
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static unsigned int __maybe_unused aarch32_check_condition(u32 opcode, u32 psr)
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{
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u32 cc_bits = opcode >> 28;
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if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
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if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
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return ARM_OPCODE_CONDTEST_PASS;
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else
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return ARM_OPCODE_CONDTEST_FAIL;
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}
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return ARM_OPCODE_CONDTEST_UNCOND;
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}
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#ifdef CONFIG_SWP_EMULATION
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/*
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* Implement emulation of the SWP/SWPB instructions using load-exclusive and
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* store-exclusive.
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*
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* Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
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* Where: Rt = destination
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* Rt2 = source
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* Rn = address
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*/
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/*
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* Error-checking SWP macros implemented using ldxr{b}/stxr{b}
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*/
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/* Arbitrary constant to ensure forward-progress of the LL/SC loop */
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#define __SWP_LL_SC_LOOPS 4
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#define __user_swpX_asm(data, addr, res, temp, temp2, B) \
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do { \
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uaccess_enable_privileged(); \
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__asm__ __volatile__( \
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" mov %w3, %w6\n" \
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"0: ldxr"B" %w2, [%4]\n" \
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"1: stxr"B" %w0, %w1, [%4]\n" \
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" cbz %w0, 2f\n" \
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" sub %w3, %w3, #1\n" \
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" cbnz %w3, 0b\n" \
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" mov %w0, %w5\n" \
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" b 3f\n" \
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"2:\n" \
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" mov %w1, %w2\n" \
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"3:\n" \
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_ASM_EXTABLE_UACCESS_ERR(0b, 3b, %w0) \
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_ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0) \
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: "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
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: "r" ((unsigned long)addr), "i" (-EAGAIN), \
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"i" (__SWP_LL_SC_LOOPS) \
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: "memory"); \
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uaccess_disable_privileged(); \
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} while (0)
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#define __user_swp_asm(data, addr, res, temp, temp2) \
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__user_swpX_asm(data, addr, res, temp, temp2, "")
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#define __user_swpb_asm(data, addr, res, temp, temp2) \
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__user_swpX_asm(data, addr, res, temp, temp2, "b")
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/*
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* Bit 22 of the instruction encoding distinguishes between
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* the SWP and SWPB variants (bit set means SWPB).
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*/
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#define TYPE_SWPB (1 << 22)
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static int emulate_swpX(unsigned int address, unsigned int *data,
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unsigned int type)
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{
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unsigned int res = 0;
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if ((type != TYPE_SWPB) && (address & 0x3)) {
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/* SWP to unaligned address not permitted */
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pr_debug("SWP instruction on unaligned pointer!\n");
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return -EFAULT;
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}
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while (1) {
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unsigned long temp, temp2;
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if (type == TYPE_SWPB)
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__user_swpb_asm(*data, address, res, temp, temp2);
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else
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__user_swp_asm(*data, address, res, temp, temp2);
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if (likely(res != -EAGAIN) || signal_pending(current))
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break;
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cond_resched();
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}
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return res;
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}
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/*
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* swp_handler logs the id of calling process, dissects the instruction, sanity
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* checks the memory location, calls emulate_swpX for the actual operation and
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* deals with fixup/error handling before returning
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*/
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static int swp_handler(struct pt_regs *regs, u32 instr)
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{
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u32 destreg, data, type, address = 0;
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const void __user *user_ptr;
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int rn, rt2, res = 0;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
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type = instr & TYPE_SWPB;
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switch (aarch32_check_condition(instr, regs->pstate)) {
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case ARM_OPCODE_CONDTEST_PASS:
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break;
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case ARM_OPCODE_CONDTEST_FAIL:
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/* Condition failed - return to next instruction */
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goto ret;
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case ARM_OPCODE_CONDTEST_UNCOND:
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/* If unconditional encoding - not a SWP, undef */
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return -EFAULT;
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default:
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return -EINVAL;
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}
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rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
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rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
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address = (u32)regs->user_regs.regs[rn];
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data = (u32)regs->user_regs.regs[rt2];
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destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
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pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
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rn, address, destreg,
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aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
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/* Check access in reasonable access range for both SWP and SWPB */
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user_ptr = (const void __user *)(unsigned long)(address & ~3);
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if (!access_ok(user_ptr, 4)) {
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pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
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address);
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goto fault;
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}
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res = emulate_swpX(address, &data, type);
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if (res == -EFAULT)
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goto fault;
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else if (res == 0)
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regs->user_regs.regs[destreg] = data;
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ret:
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if (type == TYPE_SWPB)
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trace_instruction_emulation("swpb", regs->pc);
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else
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trace_instruction_emulation("swp", regs->pc);
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pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
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current->comm, (unsigned long)current->pid, regs->pc);
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arm64_skip_faulting_instruction(regs, 4);
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return 0;
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fault:
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pr_debug("SWP{B} emulation: access caused memory abort!\n");
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arm64_notify_segfault(address);
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return 0;
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}
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static bool try_emulate_swp(struct pt_regs *regs, u32 insn)
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{
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/* SWP{B} only exists in ARM state and does not exist in Thumb */
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if (!compat_user_mode(regs) || compat_thumb_mode(regs))
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return false;
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if ((insn & 0x0fb00ff0) != 0x01000090)
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return false;
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return swp_handler(regs, insn) == 0;
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}
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static struct insn_emulation insn_swp = {
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.name = "swp",
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.status = INSN_OBSOLETE,
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.try_emulate = try_emulate_swp,
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.set_hw_mode = NULL,
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};
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#endif /* CONFIG_SWP_EMULATION */
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#ifdef CONFIG_CP15_BARRIER_EMULATION
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static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
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{
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
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switch (aarch32_check_condition(instr, regs->pstate)) {
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case ARM_OPCODE_CONDTEST_PASS:
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break;
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case ARM_OPCODE_CONDTEST_FAIL:
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/* Condition failed - return to next instruction */
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goto ret;
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case ARM_OPCODE_CONDTEST_UNCOND:
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/* If unconditional encoding - not a barrier instruction */
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return -EFAULT;
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default:
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return -EINVAL;
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}
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switch (aarch32_insn_mcr_extract_crm(instr)) {
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case 10:
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/*
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* dmb - mcr p15, 0, Rt, c7, c10, 5
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* dsb - mcr p15, 0, Rt, c7, c10, 4
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*/
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if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
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dmb(sy);
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trace_instruction_emulation(
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"mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
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} else {
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dsb(sy);
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trace_instruction_emulation(
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"mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
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}
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break;
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case 5:
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/*
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* isb - mcr p15, 0, Rt, c7, c5, 4
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*
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* Taking an exception or returning from one acts as an
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* instruction barrier. So no explicit barrier needed here.
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*/
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trace_instruction_emulation(
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"mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
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break;
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}
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ret:
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pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
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current->comm, (unsigned long)current->pid, regs->pc);
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arm64_skip_faulting_instruction(regs, 4);
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return 0;
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}
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static int cp15_barrier_set_hw_mode(bool enable)
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{
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if (enable)
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sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_CP15BEN);
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else
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_CP15BEN, 0);
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return 0;
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}
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static bool try_emulate_cp15_barrier(struct pt_regs *regs, u32 insn)
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{
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if (!compat_user_mode(regs) || compat_thumb_mode(regs))
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return false;
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if ((insn & 0x0fff0fdf) == 0x0e070f9a)
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return cp15barrier_handler(regs, insn) == 0;
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if ((insn & 0x0fff0fff) == 0x0e070f95)
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return cp15barrier_handler(regs, insn) == 0;
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return false;
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}
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static struct insn_emulation insn_cp15_barrier = {
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.name = "cp15_barrier",
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.status = INSN_DEPRECATED,
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.try_emulate = try_emulate_cp15_barrier,
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.set_hw_mode = cp15_barrier_set_hw_mode,
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};
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#endif /* CONFIG_CP15_BARRIER_EMULATION */
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#ifdef CONFIG_SETEND_EMULATION
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static int setend_set_hw_mode(bool enable)
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{
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if (!cpu_supports_mixed_endian_el0())
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return -EINVAL;
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if (enable)
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_SED, 0);
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else
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sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_SED);
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return 0;
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}
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static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
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{
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char *insn;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
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if (big_endian) {
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insn = "setend be";
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regs->pstate |= PSR_AA32_E_BIT;
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} else {
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insn = "setend le";
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regs->pstate &= ~PSR_AA32_E_BIT;
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}
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trace_instruction_emulation(insn, regs->pc);
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|
|
pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
|
||
|
|
current->comm, (unsigned long)current->pid, regs->pc);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int a32_setend_handler(struct pt_regs *regs, u32 instr)
|
||
|
|
{
|
||
|
|
int rc = compat_setend_handler(regs, (instr >> 9) & 1);
|
||
|
|
arm64_skip_faulting_instruction(regs, 4);
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int t16_setend_handler(struct pt_regs *regs, u32 instr)
|
||
|
|
{
|
||
|
|
int rc = compat_setend_handler(regs, (instr >> 3) & 1);
|
||
|
|
arm64_skip_faulting_instruction(regs, 2);
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool try_emulate_setend(struct pt_regs *regs, u32 insn)
|
||
|
|
{
|
||
|
|
if (compat_thumb_mode(regs) &&
|
||
|
|
(insn & 0xfffffff7) == 0x0000b650)
|
||
|
|
return t16_setend_handler(regs, insn) == 0;
|
||
|
|
|
||
|
|
if (compat_user_mode(regs) &&
|
||
|
|
(insn & 0xfffffdff) == 0xf1010000)
|
||
|
|
return a32_setend_handler(regs, insn) == 0;
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct insn_emulation insn_setend = {
|
||
|
|
.name = "setend",
|
||
|
|
.status = INSN_DEPRECATED,
|
||
|
|
.try_emulate = try_emulate_setend,
|
||
|
|
.set_hw_mode = setend_set_hw_mode,
|
||
|
|
};
|
||
|
|
#endif /* CONFIG_SETEND_EMULATION */
|
||
|
|
|
||
|
|
static struct insn_emulation *insn_emulations[] = {
|
||
|
|
#ifdef CONFIG_SWP_EMULATION
|
||
|
|
&insn_swp,
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_CP15_BARRIER_EMULATION
|
||
|
|
&insn_cp15_barrier,
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_SETEND_EMULATION
|
||
|
|
&insn_setend,
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
static DEFINE_MUTEX(insn_emulation_mutex);
|
||
|
|
|
||
|
|
static void enable_insn_hw_mode(void *data)
|
||
|
|
{
|
||
|
|
struct insn_emulation *insn = (struct insn_emulation *)data;
|
||
|
|
if (insn->set_hw_mode)
|
||
|
|
insn->set_hw_mode(true);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void disable_insn_hw_mode(void *data)
|
||
|
|
{
|
||
|
|
struct insn_emulation *insn = (struct insn_emulation *)data;
|
||
|
|
if (insn->set_hw_mode)
|
||
|
|
insn->set_hw_mode(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Run set_hw_mode(mode) on all active CPUs */
|
||
|
|
static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
|
||
|
|
{
|
||
|
|
if (!insn->set_hw_mode)
|
||
|
|
return -EINVAL;
|
||
|
|
if (enable)
|
||
|
|
on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
|
||
|
|
else
|
||
|
|
on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Run set_hw_mode for all insns on a starting CPU.
|
||
|
|
* Returns:
|
||
|
|
* 0 - If all the hooks ran successfully.
|
||
|
|
* -EINVAL - At least one hook is not supported by the CPU.
|
||
|
|
*/
|
||
|
|
static int run_all_insn_set_hw_mode(unsigned int cpu)
|
||
|
|
{
|
||
|
|
int rc = 0;
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Disable IRQs to serialize against an IPI from
|
||
|
|
* run_all_cpu_set_hw_mode(), ensuring the HW is programmed to the most
|
||
|
|
* recent enablement state if the two race with one another.
|
||
|
|
*/
|
||
|
|
local_irq_save(flags);
|
||
|
|
for (int i = 0; i < ARRAY_SIZE(insn_emulations); i++) {
|
||
|
|
struct insn_emulation *insn = insn_emulations[i];
|
||
|
|
bool enable = READ_ONCE(insn->current_mode) == INSN_HW;
|
||
|
|
if (insn->set_hw_mode && insn->set_hw_mode(enable)) {
|
||
|
|
pr_warn("CPU[%u] cannot support the emulation of %s",
|
||
|
|
cpu, insn->name);
|
||
|
|
rc = -EINVAL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
local_irq_restore(flags);
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int update_insn_emulation_mode(struct insn_emulation *insn,
|
||
|
|
enum insn_emulation_mode prev)
|
||
|
|
{
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
switch (prev) {
|
||
|
|
case INSN_UNDEF: /* Nothing to be done */
|
||
|
|
break;
|
||
|
|
case INSN_EMULATE:
|
||
|
|
break;
|
||
|
|
case INSN_HW:
|
||
|
|
if (!run_all_cpu_set_hw_mode(insn, false))
|
||
|
|
pr_notice("Disabled %s support\n", insn->name);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (insn->current_mode) {
|
||
|
|
case INSN_UNDEF:
|
||
|
|
break;
|
||
|
|
case INSN_EMULATE:
|
||
|
|
break;
|
||
|
|
case INSN_HW:
|
||
|
|
ret = run_all_cpu_set_hw_mode(insn, true);
|
||
|
|
if (!ret)
|
||
|
|
pr_notice("Enabled %s support\n", insn->name);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int emulation_proc_handler(struct ctl_table *table, int write,
|
||
|
|
void *buffer, size_t *lenp,
|
||
|
|
loff_t *ppos)
|
||
|
|
{
|
||
|
|
int ret = 0;
|
||
|
|
struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode);
|
||
|
|
enum insn_emulation_mode prev_mode = insn->current_mode;
|
||
|
|
|
||
|
|
mutex_lock(&insn_emulation_mutex);
|
||
|
|
ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
|
||
|
|
|
||
|
|
if (ret || !write || prev_mode == insn->current_mode)
|
||
|
|
goto ret;
|
||
|
|
|
||
|
|
ret = update_insn_emulation_mode(insn, prev_mode);
|
||
|
|
if (ret) {
|
||
|
|
/* Mode change failed, revert to previous mode. */
|
||
|
|
WRITE_ONCE(insn->current_mode, prev_mode);
|
||
|
|
update_insn_emulation_mode(insn, INSN_UNDEF);
|
||
|
|
}
|
||
|
|
ret:
|
||
|
|
mutex_unlock(&insn_emulation_mutex);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __init register_insn_emulation(struct insn_emulation *insn)
|
||
|
|
{
|
||
|
|
struct ctl_table *sysctl;
|
||
|
|
|
||
|
|
insn->min = INSN_UNDEF;
|
||
|
|
|
||
|
|
switch (insn->status) {
|
||
|
|
case INSN_DEPRECATED:
|
||
|
|
insn->current_mode = INSN_EMULATE;
|
||
|
|
/* Disable the HW mode if it was turned on at early boot time */
|
||
|
|
run_all_cpu_set_hw_mode(insn, false);
|
||
|
|
insn->max = INSN_HW;
|
||
|
|
break;
|
||
|
|
case INSN_OBSOLETE:
|
||
|
|
insn->current_mode = INSN_UNDEF;
|
||
|
|
insn->max = INSN_EMULATE;
|
||
|
|
break;
|
||
|
|
case INSN_UNAVAILABLE:
|
||
|
|
insn->current_mode = INSN_UNDEF;
|
||
|
|
insn->max = INSN_UNDEF;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Program the HW if required */
|
||
|
|
update_insn_emulation_mode(insn, INSN_UNDEF);
|
||
|
|
|
||
|
|
if (insn->status != INSN_UNAVAILABLE) {
|
||
|
|
sysctl = &insn->sysctl[0];
|
||
|
|
|
||
|
|
sysctl->mode = 0644;
|
||
|
|
sysctl->maxlen = sizeof(int);
|
||
|
|
|
||
|
|
sysctl->procname = insn->name;
|
||
|
|
sysctl->data = &insn->current_mode;
|
||
|
|
sysctl->extra1 = &insn->min;
|
||
|
|
sysctl->extra2 = &insn->max;
|
||
|
|
sysctl->proc_handler = emulation_proc_handler;
|
||
|
|
|
||
|
|
register_sysctl("abi", sysctl);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
bool try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn)
|
||
|
|
{
|
||
|
|
for (int i = 0; i < ARRAY_SIZE(insn_emulations); i++) {
|
||
|
|
struct insn_emulation *ie = insn_emulations[i];
|
||
|
|
|
||
|
|
if (ie->status == INSN_UNAVAILABLE)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* A trap may race with the mode being changed
|
||
|
|
* INSN_EMULATE<->INSN_HW. Try to emulate the instruction to
|
||
|
|
* avoid a spurious UNDEF.
|
||
|
|
*/
|
||
|
|
if (READ_ONCE(ie->current_mode) == INSN_UNDEF)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
if (ie->try_emulate(regs, insn))
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Invoked as core_initcall, which guarantees that the instruction
|
||
|
|
* emulation is ready for userspace.
|
||
|
|
*/
|
||
|
|
static int __init armv8_deprecated_init(void)
|
||
|
|
{
|
||
|
|
#ifdef CONFIG_SETEND_EMULATION
|
||
|
|
if (!system_supports_mixed_endian_el0()) {
|
||
|
|
insn_setend.status = INSN_UNAVAILABLE;
|
||
|
|
pr_info("setend instruction emulation is not supported on this system\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
for (int i = 0; i < ARRAY_SIZE(insn_emulations); i++) {
|
||
|
|
struct insn_emulation *ie = insn_emulations[i];
|
||
|
|
|
||
|
|
if (ie->status == INSN_UNAVAILABLE)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
register_insn_emulation(ie);
|
||
|
|
}
|
||
|
|
|
||
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
|
||
|
|
"arm64/isndep:starting",
|
||
|
|
run_all_insn_set_hw_mode, NULL);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
core_initcall(armv8_deprecated_init);
|