299 lines
7.6 KiB
C
299 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/kvm_host.h>
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#include <linux/random.h>
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#include <linux/memblock.h>
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#include <asm/alternative.h>
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#include <asm/debug-monitors.h>
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#include <asm/insn.h>
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#include <asm/kvm_mmu.h>
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#include <asm/memory.h>
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/*
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* The LSB of the HYP VA tag
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*/
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static u8 tag_lsb;
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/*
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* The HYP VA tag value with the region bit
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*/
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static u64 tag_val;
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static u64 va_mask;
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/*
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* Compute HYP VA by using the same computation as kern_hyp_va().
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*/
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static u64 __early_kern_hyp_va(u64 addr)
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{
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addr &= va_mask;
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addr |= tag_val << tag_lsb;
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return addr;
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}
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/*
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* Store a hyp VA <-> PA offset into a EL2-owned variable.
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*/
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static void init_hyp_physvirt_offset(void)
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{
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u64 kern_va, hyp_va;
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/* Compute the offset from the hyp VA and PA of a random symbol. */
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kern_va = (u64)lm_alias(__hyp_text_start);
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hyp_va = __early_kern_hyp_va(kern_va);
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hyp_physvirt_offset = (s64)__pa(kern_va) - (s64)hyp_va;
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}
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/*
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* We want to generate a hyp VA with the following format (with V ==
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* vabits_actual):
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*
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* 63 ... V | V-1 | V-2 .. tag_lsb | tag_lsb - 1 .. 0
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* ---------------------------------------------------------
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* | 0000000 | hyp_va_msb | random tag | kern linear VA |
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* |--------- tag_val -----------|----- va_mask ---|
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*
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* which does not conflict with the idmap regions.
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*/
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__init void kvm_compute_layout(void)
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{
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phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
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u64 hyp_va_msb;
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/* Where is my RAM region? */
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hyp_va_msb = idmap_addr & BIT(vabits_actual - 1);
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hyp_va_msb ^= BIT(vabits_actual - 1);
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tag_lsb = fls64((u64)phys_to_virt(memblock_start_of_DRAM()) ^
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(u64)(high_memory - 1));
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va_mask = GENMASK_ULL(tag_lsb - 1, 0);
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tag_val = hyp_va_msb;
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if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && tag_lsb != (vabits_actual - 1)) {
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/* We have some free bits to insert a random tag. */
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tag_val |= get_random_long() & GENMASK_ULL(vabits_actual - 2, tag_lsb);
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}
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tag_val >>= tag_lsb;
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init_hyp_physvirt_offset();
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}
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/*
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* The .hyp.reloc ELF section contains a list of kimg positions that
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* contains kimg VAs but will be accessed only in hyp execution context.
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* Convert them to hyp VAs. See gen-hyprel.c for more details.
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*/
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__init void kvm_apply_hyp_relocations(void)
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{
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int32_t *rel;
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int32_t *begin = (int32_t *)__hyp_reloc_begin;
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int32_t *end = (int32_t *)__hyp_reloc_end;
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for (rel = begin; rel < end; ++rel) {
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uintptr_t *ptr, kimg_va;
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/*
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* Each entry contains a 32-bit relative offset from itself
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* to a kimg VA position.
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*/
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ptr = (uintptr_t *)lm_alias((char *)rel + *rel);
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/* Read the kimg VA value at the relocation address. */
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kimg_va = *ptr;
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/* Convert to hyp VA and store back to the relocation address. */
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*ptr = __early_kern_hyp_va((uintptr_t)lm_alias(kimg_va));
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}
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}
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static u32 compute_instruction(int n, u32 rd, u32 rn)
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{
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u32 insn = AARCH64_BREAK_FAULT;
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switch (n) {
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case 0:
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insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
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AARCH64_INSN_VARIANT_64BIT,
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rn, rd, va_mask);
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break;
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case 1:
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/* ROR is a variant of EXTR with Rm = Rn */
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insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
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rn, rn, rd,
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tag_lsb);
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break;
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case 2:
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insn = aarch64_insn_gen_add_sub_imm(rd, rn,
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tag_val & GENMASK(11, 0),
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_ADSB_ADD);
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break;
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case 3:
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insn = aarch64_insn_gen_add_sub_imm(rd, rn,
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tag_val & GENMASK(23, 12),
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_ADSB_ADD);
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break;
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case 4:
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/* ROR is a variant of EXTR with Rm = Rn */
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insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
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rn, rn, rd, 64 - tag_lsb);
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break;
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}
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return insn;
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}
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void __init kvm_update_va_mask(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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int i;
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BUG_ON(nr_inst != 5);
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for (i = 0; i < nr_inst; i++) {
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u32 rd, rn, insn, oinsn;
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/*
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* VHE doesn't need any address translation, let's NOP
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* everything.
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*
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* Alternatively, if the tag is zero (because the layout
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* dictates it and we don't have any spare bits in the
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* address), NOP everything after masking the kernel VA.
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*/
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if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN) || (!tag_val && i > 0)) {
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updptr[i] = cpu_to_le32(aarch64_insn_gen_nop());
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continue;
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}
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oinsn = le32_to_cpu(origptr[i]);
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rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
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rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
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insn = compute_instruction(i, rd, rn);
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BUG_ON(insn == AARCH64_BREAK_FAULT);
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updptr[i] = cpu_to_le32(insn);
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}
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}
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void kvm_patch_vector_branch(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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u64 addr;
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u32 insn;
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BUG_ON(nr_inst != 4);
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if (!cpus_have_cap(ARM64_SPECTRE_V3A) ||
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WARN_ON_ONCE(cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)))
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return;
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/*
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* Compute HYP VA by using the same computation as kern_hyp_va()
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*/
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addr = __early_kern_hyp_va((u64)kvm_ksym_ref(__kvm_hyp_vector));
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/* Use PC[10:7] to branch to the same vector in KVM */
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addr |= ((u64)origptr & GENMASK_ULL(10, 7));
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/*
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* Branch over the preamble in order to avoid the initial store on
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* the stack (which we already perform in the hardening vectors).
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*/
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addr += KVM_VECTOR_PREAMBLE;
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/* movz x0, #(addr & 0xffff) */
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insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
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(u16)addr,
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0,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_ZERO);
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*updptr++ = cpu_to_le32(insn);
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/* movk x0, #((addr >> 16) & 0xffff), lsl #16 */
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insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
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(u16)(addr >> 16),
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16,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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*updptr++ = cpu_to_le32(insn);
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/* movk x0, #((addr >> 32) & 0xffff), lsl #32 */
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insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
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(u16)(addr >> 32),
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32,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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*updptr++ = cpu_to_le32(insn);
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/* br x0 */
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insn = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_0,
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AARCH64_INSN_BRANCH_NOLINK);
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*updptr++ = cpu_to_le32(insn);
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}
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static void generate_mov_q(u64 val, __le32 *origptr, __le32 *updptr, int nr_inst)
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{
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u32 insn, oinsn, rd;
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BUG_ON(nr_inst != 4);
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/* Compute target register */
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oinsn = le32_to_cpu(*origptr);
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rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
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/* movz rd, #(val & 0xffff) */
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insn = aarch64_insn_gen_movewide(rd,
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(u16)val,
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0,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_ZERO);
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*updptr++ = cpu_to_le32(insn);
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/* movk rd, #((val >> 16) & 0xffff), lsl #16 */
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insn = aarch64_insn_gen_movewide(rd,
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(u16)(val >> 16),
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16,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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*updptr++ = cpu_to_le32(insn);
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/* movk rd, #((val >> 32) & 0xffff), lsl #32 */
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insn = aarch64_insn_gen_movewide(rd,
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(u16)(val >> 32),
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32,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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*updptr++ = cpu_to_le32(insn);
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/* movk rd, #((val >> 48) & 0xffff), lsl #48 */
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insn = aarch64_insn_gen_movewide(rd,
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(u16)(val >> 48),
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48,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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*updptr++ = cpu_to_le32(insn);
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}
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void kvm_get_kimage_voffset(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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generate_mov_q(kimage_voffset, origptr, updptr, nr_inst);
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}
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void kvm_compute_final_ctr_el0(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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generate_mov_q(read_sanitised_ftr_reg(SYS_CTR_EL0),
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origptr, updptr, nr_inst);
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}
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