418 lines
11 KiB
C
418 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Page table support for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_PGTABLE_H
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#define _ASM_PGTABLE_H
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/*
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* Page table definitions for Qualcomm Hexagon processor.
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*/
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#include <asm/page.h>
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#include <asm-generic/pgtable-nopmd.h>
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/* A handy thing to have if one has the RAM. Declared in head.S */
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extern unsigned long empty_zero_page;
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/*
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* The PTE model described here is that of the Hexagon Virtual Machine,
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* which autonomously walks 2-level page tables. At a lower level, we
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* also describe the RISCish software-loaded TLB entry structure of
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* the underlying Hexagon processor. A kernel built to run on the
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* virtual machine has no need to know about the underlying hardware.
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*/
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#include <asm/vm_mmu.h>
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/*
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* To maximize the comfort level for the PTE manipulation macros,
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* define the "well known" architecture-specific bits.
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*/
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#define _PAGE_READ __HVM_PTE_R
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#define _PAGE_WRITE __HVM_PTE_W
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#define _PAGE_EXECUTE __HVM_PTE_X
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#define _PAGE_USER __HVM_PTE_U
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/*
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* We have a total of 4 "soft" bits available in the abstract PTE.
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* The two mandatory software bits are Dirty and Accessed.
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* To make nonlinear swap work according to the more recent
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* model, we want a low order "Present" bit to indicate whether
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* the PTE describes MMU programming or swap space.
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*/
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#define _PAGE_PRESENT (1<<0)
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#define _PAGE_DIRTY (1<<1)
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#define _PAGE_ACCESSED (1<<2)
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/*
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* For now, let's say that Valid and Present are the same thing.
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* Alternatively, we could say that it's the "or" of R, W, and X
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* permissions.
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*/
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#define _PAGE_VALID _PAGE_PRESENT
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/*
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* We're not defining _PAGE_GLOBAL here, since there's no concept
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* of global pages or ASIDs exposed to the Hexagon Virtual Machine,
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* and we want to use the same page table structures and macros in
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* the native kernel as we do in the virtual machine kernel.
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* So we'll put up with a bit of inefficiency for now...
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*/
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/* We borrow bit 6 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE (1<<6)
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/*
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* Top "FOURTH" level (pgd), which for the Hexagon VM is really
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* only the second from the bottom, pgd and pud both being collapsed.
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* Each entry represents 4MB of virtual address space, 4K of table
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* thus maps the full 4GB.
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*/
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#define PGDIR_SHIFT 22
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#define PTRS_PER_PGD 1024
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#ifdef CONFIG_PAGE_SIZE_4KB
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#define PTRS_PER_PTE 1024
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#endif
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#ifdef CONFIG_PAGE_SIZE_16KB
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#define PTRS_PER_PTE 256
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#endif
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#ifdef CONFIG_PAGE_SIZE_64KB
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#define PTRS_PER_PTE 64
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#endif
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#ifdef CONFIG_PAGE_SIZE_256KB
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#define PTRS_PER_PTE 16
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#endif
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#ifdef CONFIG_PAGE_SIZE_1MB
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#define PTRS_PER_PTE 4
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#endif
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/* Any bigger and the PTE disappears. */
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#define pgd_ERROR(e) \
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printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__,\
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pgd_val(e))
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/*
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* Page Protection Constants. Includes (in this variant) cache attributes.
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*/
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extern unsigned long _dflt_cache_att;
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#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | \
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_dflt_cache_att)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | \
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_PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att)
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#define PAGE_COPY PAGE_READONLY
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#define PAGE_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
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_PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att)
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#define PAGE_COPY_EXEC PAGE_EXEC
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \
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_PAGE_EXECUTE | _PAGE_WRITE | _dflt_cache_att)
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | \
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_PAGE_WRITE | _PAGE_EXECUTE | _dflt_cache_att)
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/*
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* Aliases for mapping mmap() protection bits to page protections.
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* These get used for static initialization, so using the _dflt_cache_att
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* variable for the default cache attribute isn't workable. If the
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* default gets changed at boot time, the boot option code has to
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* update data structures like the protaction_map[] array.
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*/
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#define CACHEDEF (CACHE_DEFAULT << 6)
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* located in head.S */
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/* HUGETLB not working currently */
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#ifdef CONFIG_HUGETLB_PAGE
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#define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE)
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#endif
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/*
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* For now, assume that higher-level code will do TLB/MMU invalidations
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* and don't insert that overhead into this low-level function.
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*/
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extern void sync_icache_dcache(pte_t pte);
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#define pte_present_exec_user(pte) \
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((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \
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(_PAGE_EXECUTE | _PAGE_USER))
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static inline void set_pte(pte_t *ptep, pte_t pteval)
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{
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/* should really be using pte_exec, if it weren't declared later. */
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if (pte_present_exec_user(pteval))
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sync_icache_dcache(pteval);
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*ptep = pteval;
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}
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/*
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* For the Hexagon Virtual Machine MMU (or its emulation), a null/invalid
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* L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE
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* (Linux PTE), the key is to have bits 11..9 all zero. We'd use 0x7
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* as a universal null entry, but some of those least significant bits
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* are interpreted by software.
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*/
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#define _NULL_PMD 0x7
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#define _NULL_PTE 0x0
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static inline void pmd_clear(pmd_t *pmd_entry_ptr)
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{
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pmd_val(*pmd_entry_ptr) = _NULL_PMD;
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}
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/*
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* Conveniently, a null PTE value is invalid.
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*/
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static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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pte_val(*ptep) = _NULL_PTE;
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}
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/**
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* pmd_none - check if pmd_entry is mapped
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* @pmd_entry: pmd entry
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*
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* MIPS checks it against that "invalid pte table" thing.
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*/
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static inline int pmd_none(pmd_t pmd)
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{
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return pmd_val(pmd) == _NULL_PMD;
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}
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/**
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* pmd_present - is there a page table behind this?
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* Essentially the inverse of pmd_none. We maybe
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* save an inline instruction by defining it this
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* way, instead of simply "!pmd_none".
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*/
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static inline int pmd_present(pmd_t pmd)
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{
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return pmd_val(pmd) != (unsigned long)_NULL_PMD;
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}
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/**
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* pmd_bad - check if a PMD entry is "bad". That might mean swapped out.
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* As we have no known cause of badness, it's null, as it is for many
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* architectures.
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*/
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static inline int pmd_bad(pmd_t pmd)
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{
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return 0;
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}
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/*
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* pmd_pfn - converts a PMD entry to a page frame number
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*/
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#define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT)
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/*
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* pmd_page - converts a PMD entry to a page pointer
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*/
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#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
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/**
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* pte_none - check if pte is mapped
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* @pte: pte_t entry
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*/
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static inline int pte_none(pte_t pte)
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{
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return pte_val(pte) == _NULL_PTE;
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};
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/*
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* pte_present - check if page is present
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*/
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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/* mk_pte - make a PTE out of a page pointer and protection bits */
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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/* pte_page - returns a page (frame pointer/descriptor?) based on a PTE */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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/* pte_mkold - mark PTE as not recently accessed */
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static inline pte_t pte_mkold(pte_t pte)
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{
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pte_val(pte) &= ~_PAGE_ACCESSED;
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return pte;
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}
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/* pte_mkyoung - mark PTE as recently accessed */
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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pte_val(pte) |= _PAGE_ACCESSED;
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return pte;
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}
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/* pte_mkclean - mark page as in sync with backing store */
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static inline pte_t pte_mkclean(pte_t pte)
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{
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pte_val(pte) &= ~_PAGE_DIRTY;
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return pte;
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}
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/* pte_mkdirty - mark page as modified */
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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pte_val(pte) |= _PAGE_DIRTY;
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return pte;
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}
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/* pte_young - "is PTE marked as accessed"? */
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static inline int pte_young(pte_t pte)
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{
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return pte_val(pte) & _PAGE_ACCESSED;
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}
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/* pte_dirty - "is PTE dirty?" */
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static inline int pte_dirty(pte_t pte)
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{
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return pte_val(pte) & _PAGE_DIRTY;
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}
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/* pte_modify - set protection bits on PTE */
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static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
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{
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pte_val(pte) &= PAGE_MASK;
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pte_val(pte) |= pgprot_val(prot);
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return pte;
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}
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/* pte_wrprotect - mark page as not writable */
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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pte_val(pte) &= ~_PAGE_WRITE;
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return pte;
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}
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/* pte_mkwrite - mark page as writable */
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte_val(pte) |= _PAGE_WRITE;
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return pte;
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}
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/* pte_mkexec - mark PTE as executable */
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static inline pte_t pte_mkexec(pte_t pte)
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{
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pte_val(pte) |= _PAGE_EXECUTE;
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return pte;
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}
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/* pte_read - "is PTE marked as readable?" */
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static inline int pte_read(pte_t pte)
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{
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return pte_val(pte) & _PAGE_READ;
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}
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/* pte_write - "is PTE marked as writable?" */
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static inline int pte_write(pte_t pte)
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{
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return pte_val(pte) & _PAGE_WRITE;
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}
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/* pte_exec - "is PTE marked as executable?" */
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static inline int pte_exec(pte_t pte)
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{
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return pte_val(pte) & _PAGE_EXECUTE;
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}
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/* __pte_to_swp_entry - extract swap entry from PTE */
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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/* __swp_entry_to_pte - extract PTE from swap entry */
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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/* pfn_pte - convert page number and protection value to page table entry */
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#define pfn_pte(pfn, pgprot) __pte((pfn << PAGE_SHIFT) | pgprot_val(pgprot))
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/* pte_pfn - convert pte to page frame number */
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
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/*
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* set_pte_at - update page table and do whatever magic may be
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* necessary to make the underlying hardware/firmware take note.
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*
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* VM may require a virtual instruction to alert the MMU.
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*/
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#define set_pte_at(mm, addr, ptep, pte) set_pte(ptep, pte)
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static inline unsigned long pmd_page_vaddr(pmd_t pmd)
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{
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return (unsigned long)__va(pmd_val(pmd) & PAGE_MASK);
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}
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/* ZERO_PAGE - returns the globally shared zero page */
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#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
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/*
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* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
|
||
|
|
* are !pte_none() && !pte_present().
|
||
|
|
*
|
||
|
|
* Swap/file PTE definitions. If _PAGE_PRESENT is zero, the rest of the PTE is
|
||
|
|
* interpreted as swap information. The remaining free bits are interpreted as
|
||
|
|
* listed below. Rather than have the TLB fill handler test
|
||
|
|
* _PAGE_PRESENT, we're going to reserve the permissions bits and set them to
|
||
|
|
* all zeros for swap entries, which speeds up the miss handler at the cost of
|
||
|
|
* 3 bits of offset. That trade-off can be revisited if necessary, but Hexagon
|
||
|
|
* processor architecture and target applications suggest a lot of TLB misses
|
||
|
|
* and not much swap space.
|
||
|
|
*
|
||
|
|
* Format of swap PTE:
|
||
|
|
* bit 0: Present (zero)
|
||
|
|
* bits 1-5: swap type (arch independent layer uses 5 bits max)
|
||
|
|
* bit 6: exclusive marker
|
||
|
|
* bits 7-9: bits 2:0 of offset
|
||
|
|
* bits 10-12: effectively _PAGE_PROTNONE (all zero)
|
||
|
|
* bits 13-31: bits 21:3 of swap offset
|
||
|
|
*
|
||
|
|
* The split offset makes some of the following macros a little gnarly,
|
||
|
|
* but there's plenty of precedent for this sort of thing.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Used for swap PTEs */
|
||
|
|
#define __swp_type(swp_pte) (((swp_pte).val >> 1) & 0x1f)
|
||
|
|
|
||
|
|
#define __swp_offset(swp_pte) \
|
||
|
|
((((swp_pte).val >> 7) & 0x7) | (((swp_pte).val >> 10) & 0x3ffff8))
|
||
|
|
|
||
|
|
#define __swp_entry(type, offset) \
|
||
|
|
((swp_entry_t) { \
|
||
|
|
(((type & 0x1f) << 1) | \
|
||
|
|
((offset & 0x3ffff8) << 10) | ((offset & 0x7) << 7)) })
|
||
|
|
|
||
|
|
static inline int pte_swp_exclusive(pte_t pte)
|
||
|
|
{
|
||
|
|
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline pte_t pte_swp_mkexclusive(pte_t pte)
|
||
|
|
{
|
||
|
|
pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
|
||
|
|
return pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline pte_t pte_swp_clear_exclusive(pte_t pte)
|
||
|
|
{
|
||
|
|
pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
|
||
|
|
return pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|