159 lines
3.2 KiB
C
159 lines
3.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Spinlock support for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_SPINLOCK_H
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#define _ASM_SPINLOCK_H
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#include <asm/irqflags.h>
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#include <asm/barrier.h>
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#include <asm/processor.h>
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/*
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* This file is pulled in for SMP builds.
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* Really need to check all the barrier stuff for "true" SMP
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*/
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/*
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* Read locks:
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* - load the lock value
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* - increment it
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* - if the lock value is still negative, go back and try again.
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* - unsuccessful store is unsuccessful. Go back and try again. Loser.
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* - successful store new lock value if positive -> lock acquired
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*/
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static inline void arch_read_lock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0);\n"
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" { P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
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" { if (!P3) jump 1b; }\n"
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" memw_locked(%0,P3) = R6;\n"
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" { if (!P3) jump 1b; }\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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static inline void arch_read_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0);\n"
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" R6 = add(R6,#-1);\n"
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" memw_locked(%0,P3) = R6\n"
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" if (!P3) jump 1b;\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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/* I think this returns 0 on fail, 1 on success. */
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static inline int arch_read_trylock(arch_rwlock_t *lock)
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{
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int temp;
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__asm__ __volatile__(
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" R6 = memw_locked(%1);\n"
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" { %0 = #0; P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
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" { if (!P3) jump 1f; }\n"
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" memw_locked(%1,P3) = R6;\n"
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" { %0 = P3 }\n"
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"1:\n"
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: "=&r" (temp)
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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return temp;
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}
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/* Stuffs a -1 in the lock value? */
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static inline void arch_write_lock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0)\n"
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" { P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
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" { if (!P3) jump 1b; }\n"
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" memw_locked(%0,P3) = R6;\n"
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" { if (!P3) jump 1b; }\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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static inline int arch_write_trylock(arch_rwlock_t *lock)
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{
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int temp;
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__asm__ __volatile__(
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" R6 = memw_locked(%1)\n"
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" { %0 = #0; P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
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" { if (!P3) jump 1f; }\n"
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" memw_locked(%1,P3) = R6;\n"
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" %0 = P3;\n"
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"1:\n"
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: "=&r" (temp)
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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return temp;
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}
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static inline void arch_write_unlock(arch_rwlock_t *lock)
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{
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smp_mb();
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lock->lock = 0;
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}
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0);\n"
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" P3 = cmp.eq(R6,#0);\n"
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" { if (!P3) jump 1b; R6 = #1; }\n"
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" memw_locked(%0,P3) = R6;\n"
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" { if (!P3) jump 1b; }\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_mb();
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lock->lock = 0;
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}
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static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
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{
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int temp;
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__asm__ __volatile__(
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" R6 = memw_locked(%1);\n"
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" P3 = cmp.eq(R6,#0);\n"
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" { if (!P3) jump 1f; R6 = #1; %0 = #0; }\n"
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" memw_locked(%1,P3) = R6;\n"
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" %0 = P3;\n"
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"1:\n"
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: "=&r" (temp)
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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return temp;
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}
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/*
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* SMP spinlocks are intended to allow only a single CPU at the lock
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*/
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#define arch_spin_is_locked(x) ((x)->lock != 0)
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#endif
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