146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_HW_BREAKPOINT_H
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#define __ASM_HW_BREAKPOINT_H
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#include <asm/loongarch.h>
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#ifdef __KERNEL__
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/* Breakpoint */
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#define LOONGARCH_BREAKPOINT_EXECUTE (0 << 0)
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/* Watchpoints */
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#define LOONGARCH_BREAKPOINT_LOAD (1 << 0)
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#define LOONGARCH_BREAKPOINT_STORE (1 << 1)
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struct arch_hw_breakpoint_ctrl {
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u32 __reserved : 28,
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len : 2,
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type : 2;
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};
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struct arch_hw_breakpoint {
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u64 address;
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u64 mask;
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struct arch_hw_breakpoint_ctrl ctrl;
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};
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/* Lengths */
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#define LOONGARCH_BREAKPOINT_LEN_1 0b11
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#define LOONGARCH_BREAKPOINT_LEN_2 0b10
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#define LOONGARCH_BREAKPOINT_LEN_4 0b01
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#define LOONGARCH_BREAKPOINT_LEN_8 0b00
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/*
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* Limits.
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* Changing these will require modifications to the register accessors.
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*/
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#define LOONGARCH_MAX_BRP 8
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#define LOONGARCH_MAX_WRP 8
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/* Virtual debug register bases. */
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#define CSR_CFG_ADDR 0
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#define CSR_CFG_MASK (CSR_CFG_ADDR + LOONGARCH_MAX_BRP)
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#define CSR_CFG_CTRL (CSR_CFG_MASK + LOONGARCH_MAX_BRP)
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#define CSR_CFG_ASID (CSR_CFG_CTRL + LOONGARCH_MAX_WRP)
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/* Debug register names. */
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#define LOONGARCH_CSR_NAME_ADDR ADDR
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#define LOONGARCH_CSR_NAME_MASK MASK
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#define LOONGARCH_CSR_NAME_CTRL CTRL
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#define LOONGARCH_CSR_NAME_ASID ASID
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/* Accessor macros for the debug registers. */
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#define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \
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do { \
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if (T == 0) \
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VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \
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else \
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VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \
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} while (0)
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#define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \
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do { \
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if (T == 0) \
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csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \
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else \
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csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
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} while (0)
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/* Exact number */
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#define CSR_FWPC_NUM 0x3f
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#define CSR_MWPC_NUM 0x3f
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#define CTRL_PLV_ENABLE 0x1e
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#define MWPnCFG3_LoadEn 8
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#define MWPnCFG3_StoreEn 9
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#define MWPnCFG3_Type_mask 0x3
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#define MWPnCFG3_Size_mask 0x3
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static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
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{
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return (ctrl.len << 10) | (ctrl.type << 8);
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}
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static inline void decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl *ctrl)
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{
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reg >>= 8;
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ctrl->type = reg & MWPnCFG3_Type_mask;
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reg >>= 2;
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ctrl->len = reg & MWPnCFG3_Size_mask;
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}
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struct task_struct;
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struct notifier_block;
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struct perf_event;
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struct perf_event_attr;
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extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
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int *gen_len, int *gen_type, int *offset);
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extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
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extern int hw_breakpoint_arch_parse(struct perf_event *bp,
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const struct perf_event_attr *attr,
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struct arch_hw_breakpoint *hw);
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extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data);
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extern int arch_install_hw_breakpoint(struct perf_event *bp);
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extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
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extern int hw_breakpoint_slots(int type);
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extern void hw_breakpoint_pmu_read(struct perf_event *bp);
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void breakpoint_handler(struct pt_regs *regs);
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void watchpoint_handler(struct pt_regs *regs);
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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extern void ptrace_hw_copy_thread(struct task_struct *task);
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extern void hw_breakpoint_thread_switch(struct task_struct *next);
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#else
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static inline void ptrace_hw_copy_thread(struct task_struct *task)
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{
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}
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static inline void hw_breakpoint_thread_switch(struct task_struct *next)
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{
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}
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#endif
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/* Determine number of BRP registers available. */
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static inline int get_num_brps(void)
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{
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return csr_read64(LOONGARCH_CSR_FWPC) & CSR_FWPC_NUM;
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}
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/* Determine number of WRP registers available. */
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static inline int get_num_wrps(void)
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{
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return csr_read64(LOONGARCH_CSR_MWPC) & CSR_MWPC_NUM;
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}
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#endif /* __KERNEL__ */
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#endif /* __ASM_BREAKPOINT_H */
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