354 lines
9.8 KiB
Plaintext
354 lines
9.8 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Device Tree Generator version: 1.1
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*
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* (C) Copyright 2007-2008 Xilinx, Inc.
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* (C) Copyright 2007-2009 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
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*
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* XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,microblaze";
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model = "testing";
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DDR2_SDRAM: memory@90000000 {
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device_type = "memory";
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reg = < 0x90000000 0x10000000 >;
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} ;
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aliases {
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ethernet0 = &Hard_Ethernet_MAC;
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serial0 = &RS232_Uart_1;
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} ;
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chosen {
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bootargs = "console=ttyUL0,115200 highres=on";
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stdout-path = "/plb@0/serial@84000000";
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} ;
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cpus {
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#address-cells = <1>;
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#cpus = <0x1>;
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#size-cells = <0>;
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microblaze_0: cpu@0 {
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clock-frequency = <125000000>;
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compatible = "xlnx,microblaze-7.10.d";
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d-cache-baseaddr = <0x90000000>;
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d-cache-highaddr = <0x9fffffff>;
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d-cache-line-size = <0x10>;
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d-cache-size = <0x2000>;
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device_type = "cpu";
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i-cache-baseaddr = <0x90000000>;
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i-cache-highaddr = <0x9fffffff>;
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i-cache-line-size = <0x10>;
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i-cache-size = <0x2000>;
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model = "microblaze,7.10.d";
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reg = <0>;
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timebase-frequency = <125000000>;
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xlnx,addr-tag-bits = <0xf>;
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xlnx,allow-dcache-wr = <0x1>;
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xlnx,allow-icache-wr = <0x1>;
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xlnx,area-optimized = <0x0>;
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xlnx,cache-byte-size = <0x2000>;
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xlnx,d-lmb = <0x1>;
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xlnx,d-opb = <0x0>;
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xlnx,d-plb = <0x1>;
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xlnx,data-size = <0x20>;
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xlnx,dcache-addr-tag = <0xf>;
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xlnx,dcache-always-used = <0x1>;
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xlnx,dcache-byte-size = <0x2000>;
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xlnx,dcache-line-len = <0x4>;
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xlnx,dcache-use-fsl = <0x1>;
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xlnx,debug-enabled = <0x1>;
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xlnx,div-zero-exception = <0x1>;
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xlnx,dopb-bus-exception = <0x0>;
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xlnx,dynamic-bus-sizing = <0x1>;
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xlnx,edge-is-positive = <0x1>;
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xlnx,family = "virtex5";
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xlnx,endianness = <0x1>;
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xlnx,fpu-exception = <0x1>;
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xlnx,fsl-data-size = <0x20>;
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xlnx,fsl-exception = <0x0>;
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xlnx,fsl-links = <0x0>;
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xlnx,i-lmb = <0x1>;
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xlnx,i-opb = <0x0>;
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xlnx,i-plb = <0x1>;
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xlnx,icache-always-used = <0x1>;
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xlnx,icache-line-len = <0x4>;
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xlnx,icache-use-fsl = <0x1>;
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xlnx,ill-opcode-exception = <0x1>;
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xlnx,instance = "microblaze_0";
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xlnx,interconnect = <0x1>;
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xlnx,interrupt-is-edge = <0x0>;
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xlnx,iopb-bus-exception = <0x0>;
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xlnx,mmu-dtlb-size = <0x4>;
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xlnx,mmu-itlb-size = <0x2>;
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xlnx,mmu-tlb-access = <0x3>;
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xlnx,mmu-zones = <0x10>;
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xlnx,number-of-pc-brk = <0x1>;
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xlnx,number-of-rd-addr-brk = <0x0>;
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xlnx,number-of-wr-addr-brk = <0x0>;
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xlnx,opcode-0x0-illegal = <0x1>;
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xlnx,pvr = <0x2>;
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xlnx,pvr-user1 = <0x0>;
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xlnx,pvr-user2 = <0x0>;
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xlnx,reset-msr = <0x0>;
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xlnx,sco = <0x0>;
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xlnx,unaligned-exceptions = <0x1>;
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xlnx,use-barrel = <0x1>;
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xlnx,use-dcache = <0x1>;
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xlnx,use-div = <0x1>;
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xlnx,use-ext-brk = <0x1>;
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xlnx,use-ext-nm-brk = <0x1>;
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xlnx,use-extended-fsl-instr = <0x0>;
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xlnx,use-fpu = <0x2>;
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xlnx,use-hw-mul = <0x2>;
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xlnx,use-icache = <0x1>;
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xlnx,use-interrupt = <0x1>;
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xlnx,use-mmu = <0x3>;
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xlnx,use-msr-instr = <0x1>;
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xlnx,use-pcmp-instr = <0x1>;
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} ;
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} ;
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mb_plb: plb@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
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ranges ;
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FLASH: flash@a0000000 {
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bank-width = <2>;
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compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
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reg = < 0xa0000000 0x2000000 >;
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xlnx,family = "virtex5";
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xlnx,include-datawidth-matching-0 = <0x1>;
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xlnx,include-datawidth-matching-1 = <0x0>;
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xlnx,include-datawidth-matching-2 = <0x0>;
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xlnx,include-datawidth-matching-3 = <0x0>;
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xlnx,include-negedge-ioregs = <0x0>;
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xlnx,include-plb-ipif = <0x1>;
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xlnx,include-wrbuf = <0x1>;
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xlnx,max-mem-width = <0x10>;
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xlnx,mch-native-dwidth = <0x20>;
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xlnx,mch-plb-clk-period-ps = <0x1f40>;
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xlnx,mch-splb-awidth = <0x20>;
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xlnx,mch0-accessbuf-depth = <0x10>;
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xlnx,mch0-protocol = <0x0>;
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xlnx,mch0-rddatabuf-depth = <0x10>;
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xlnx,mch1-accessbuf-depth = <0x10>;
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xlnx,mch1-protocol = <0x0>;
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xlnx,mch1-rddatabuf-depth = <0x10>;
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xlnx,mch2-accessbuf-depth = <0x10>;
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xlnx,mch2-protocol = <0x0>;
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xlnx,mch2-rddatabuf-depth = <0x10>;
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xlnx,mch3-accessbuf-depth = <0x10>;
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xlnx,mch3-protocol = <0x0>;
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xlnx,mch3-rddatabuf-depth = <0x10>;
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xlnx,mem0-width = <0x10>;
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xlnx,mem1-width = <0x20>;
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xlnx,mem2-width = <0x20>;
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xlnx,mem3-width = <0x20>;
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xlnx,num-banks-mem = <0x1>;
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xlnx,num-channels = <0x0>;
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xlnx,priority-mode = <0x0>;
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xlnx,synch-mem-0 = <0x0>;
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xlnx,synch-mem-1 = <0x0>;
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xlnx,synch-mem-2 = <0x0>;
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xlnx,synch-mem-3 = <0x0>;
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xlnx,synch-pipedelay-0 = <0x2>;
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xlnx,synch-pipedelay-1 = <0x2>;
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xlnx,synch-pipedelay-2 = <0x2>;
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xlnx,synch-pipedelay-3 = <0x2>;
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xlnx,tavdv-ps-mem-0 = <0x1adb0>;
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xlnx,tavdv-ps-mem-1 = <0x3a98>;
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xlnx,tavdv-ps-mem-2 = <0x3a98>;
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xlnx,tavdv-ps-mem-3 = <0x3a98>;
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xlnx,tcedv-ps-mem-0 = <0x1adb0>;
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xlnx,tcedv-ps-mem-1 = <0x3a98>;
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xlnx,tcedv-ps-mem-2 = <0x3a98>;
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xlnx,tcedv-ps-mem-3 = <0x3a98>;
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xlnx,thzce-ps-mem-0 = <0x88b8>;
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xlnx,thzce-ps-mem-1 = <0x1b58>;
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xlnx,thzce-ps-mem-2 = <0x1b58>;
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xlnx,thzce-ps-mem-3 = <0x1b58>;
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xlnx,thzoe-ps-mem-0 = <0x1b58>;
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xlnx,thzoe-ps-mem-1 = <0x1b58>;
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xlnx,thzoe-ps-mem-2 = <0x1b58>;
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xlnx,thzoe-ps-mem-3 = <0x1b58>;
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xlnx,tlzwe-ps-mem-0 = <0x88b8>;
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xlnx,tlzwe-ps-mem-1 = <0x0>;
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xlnx,tlzwe-ps-mem-2 = <0x0>;
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xlnx,tlzwe-ps-mem-3 = <0x0>;
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xlnx,twc-ps-mem-0 = <0x2af8>;
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xlnx,twc-ps-mem-1 = <0x3a98>;
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xlnx,twc-ps-mem-2 = <0x3a98>;
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xlnx,twc-ps-mem-3 = <0x3a98>;
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xlnx,twp-ps-mem-0 = <0x11170>;
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xlnx,twp-ps-mem-1 = <0x2ee0>;
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xlnx,twp-ps-mem-2 = <0x2ee0>;
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xlnx,twp-ps-mem-3 = <0x2ee0>;
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xlnx,xcl0-linesize = <0x4>;
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xlnx,xcl0-writexfer = <0x1>;
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xlnx,xcl1-linesize = <0x4>;
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xlnx,xcl1-writexfer = <0x1>;
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xlnx,xcl2-linesize = <0x4>;
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xlnx,xcl2-writexfer = <0x1>;
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xlnx,xcl3-linesize = <0x4>;
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xlnx,xcl3-writexfer = <0x1>;
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} ;
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Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,compound";
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ranges ;
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ethernet@81c00000 {
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compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 5 2 >;
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llink-connected = <&PIM3>;
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local-mac-address = [ 00 0a 35 00 00 00 ];
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reg = < 0x81c00000 0x40 >;
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xlnx,bus2core-clk-ratio = <0x1>;
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xlnx,phy-type = <0x1>;
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xlnx,phyaddr = <0x1>;
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xlnx,rxcsum = <0x0>;
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xlnx,rxfifo = <0x1000>;
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xlnx,temac-type = <0x0>;
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xlnx,txcsum = <0x0>;
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xlnx,txfifo = <0x1000>;
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} ;
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} ;
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IIC_EEPROM: i2c@81600000 {
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compatible = "xlnx,xps-iic-2.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 6 2 >;
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reg = < 0x81600000 0x10000 >;
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xlnx,clk-freq = <0x7735940>;
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xlnx,family = "virtex5";
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xlnx,gpo-width = <0x1>;
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xlnx,iic-freq = <0x186a0>;
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xlnx,scl-inertial-delay = <0x0>;
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xlnx,sda-inertial-delay = <0x0>;
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xlnx,ten-bit-adr = <0x0>;
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} ;
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LEDs_8Bit: gpio@81400000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 7 2 >;
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reg = < 0x81400000 0x10000 >;
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xlnx,all-inputs = <0x0>;
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xlnx,all-inputs-2 = <0x0>;
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xlnx,dout-default = <0x0>;
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xlnx,dout-default-2 = <0x0>;
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xlnx,family = "virtex5";
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xlnx,gpio-width = <0x8>;
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xlnx,interrupt-present = <0x1>;
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xlnx,is-bidir = <0x1>;
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xlnx,is-bidir-2 = <0x1>;
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xlnx,is-dual = <0x0>;
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xlnx,tri-default = <0xffffffff>;
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xlnx,tri-default-2 = <0xffffffff>;
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#gpio-cells = <2>;
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gpio-controller;
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} ;
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gpio-leds {
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compatible = "gpio-leds";
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heartbeat {
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label = "Heartbeat";
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gpios = <&LEDs_8Bit 4 1>;
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linux,default-trigger = "heartbeat";
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};
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yellow {
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label = "Yellow";
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gpios = <&LEDs_8Bit 5 1>;
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};
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red {
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label = "Red";
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gpios = <&LEDs_8Bit 6 1>;
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};
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green {
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label = "Green";
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gpios = <&LEDs_8Bit 7 1>;
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};
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} ;
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gpio-restart {
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compatible = "gpio-restart";
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/*
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* FIXME: is this active low or active high?
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* the current flag (1) indicates active low.
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* delay measures are templates, should be adjusted
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* to datasheet or trial-and-error with real hardware.
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*/
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gpios = <&LEDs_8Bit 2 1>;
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active-delay = <100>;
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inactive-delay = <10>;
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wait-delay = <100>;
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};
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RS232_Uart_1: serial@84000000 {
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clock-frequency = <125000000>;
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compatible = "xlnx,xps-uartlite-1.00.a";
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current-speed = <115200>;
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device_type = "serial";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 8 0 >;
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port-number = <0>;
|
||
|
|
reg = < 0x84000000 0x10000 >;
|
||
|
|
xlnx,baudrate = <0x1c200>;
|
||
|
|
xlnx,data-bits = <0x8>;
|
||
|
|
xlnx,family = "virtex5";
|
||
|
|
xlnx,odd-parity = <0x0>;
|
||
|
|
xlnx,use-parity = <0x0>;
|
||
|
|
} ;
|
||
|
|
debug_module: debug@84400000 {
|
||
|
|
compatible = "xlnx,mdm-1.00.d";
|
||
|
|
reg = < 0x84400000 0x10000 >;
|
||
|
|
xlnx,family = "virtex5";
|
||
|
|
xlnx,interconnect = <0x1>;
|
||
|
|
xlnx,jtag-chain = <0x2>;
|
||
|
|
xlnx,mb-dbg-ports = <0x1>;
|
||
|
|
xlnx,uart-width = <0x8>;
|
||
|
|
xlnx,use-uart = <0x1>;
|
||
|
|
xlnx,write-fsl-ports = <0x0>;
|
||
|
|
} ;
|
||
|
|
mpmc@90000000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "xlnx,mpmc-4.02.a";
|
||
|
|
ranges ;
|
||
|
|
PIM3: sdma@84600180 {
|
||
|
|
compatible = "xlnx,ll-dma-1.00.a";
|
||
|
|
interrupt-parent = <&xps_intc_0>;
|
||
|
|
interrupts = < 2 2 1 2 >;
|
||
|
|
reg = < 0x84600180 0x80 >;
|
||
|
|
} ;
|
||
|
|
} ;
|
||
|
|
xps_intc_0: interrupt-controller@81800000 {
|
||
|
|
#interrupt-cells = <0x2>;
|
||
|
|
compatible = "xlnx,xps-intc-1.00.a";
|
||
|
|
interrupt-controller ;
|
||
|
|
reg = < 0x81800000 0x10000 >;
|
||
|
|
xlnx,kind-of-intr = <0x100>;
|
||
|
|
xlnx,num-intr-inputs = <0x9>;
|
||
|
|
} ;
|
||
|
|
xps_timer_1: timer@83c00000 {
|
||
|
|
compatible = "xlnx,xps-timer-1.00.a";
|
||
|
|
interrupt-parent = <&xps_intc_0>;
|
||
|
|
interrupts = < 3 2 >;
|
||
|
|
reg = < 0x83c00000 0x10000 >;
|
||
|
|
xlnx,count-width = <0x20>;
|
||
|
|
xlnx,one-timer-only = <0x0>;
|
||
|
|
} ;
|
||
|
|
} ;
|
||
|
|
} ;
|