172 lines
4.0 KiB
C
172 lines
4.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/fs.h>
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#include <linux/interrupt.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-ciu-defs.h>
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#include <asm/octeon/cvmx.h>
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#include <linux/debugfs.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#define TIMER_NUM 3
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static bool reset_stats;
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struct latency_info {
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u64 io_interval;
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u64 cpu_interval;
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u64 timer_start1;
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u64 timer_start2;
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u64 max_latency;
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u64 min_latency;
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u64 latency_sum;
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u64 average_latency;
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u64 interrupt_cnt;
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};
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static struct latency_info li;
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static struct dentry *dir;
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static int oct_ilm_show(struct seq_file *m, void *v)
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{
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u64 cpuclk, avg, max, min;
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struct latency_info curr_li = li;
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cpuclk = octeon_get_clock_rate();
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max = (curr_li.max_latency * 1000000000) / cpuclk;
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min = (curr_li.min_latency * 1000000000) / cpuclk;
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avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt);
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seq_printf(m, "cnt: %10lld, avg: %7lld ns, max: %7lld ns, min: %7lld ns\n",
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curr_li.interrupt_cnt, avg, max, min);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(oct_ilm);
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static int reset_statistics(void *data, u64 value)
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{
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reset_stats = true;
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n");
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static void init_debugfs(void)
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{
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dir = debugfs_create_dir("oct_ilm", 0);
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debugfs_create_file("statistics", 0222, dir, NULL, &oct_ilm_fops);
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debugfs_create_file("reset", 0222, dir, NULL, &reset_statistics_ops);
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}
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static void init_latency_info(struct latency_info *li, int startup)
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{
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/* interval in milli seconds after which the interrupt will
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* be triggered
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*/
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int interval = 1;
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if (startup) {
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/* Calculating by the amounts io clock and cpu clock would
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* increment in interval amount of ms
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*/
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li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000;
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li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000;
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}
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li->timer_start1 = 0;
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li->timer_start2 = 0;
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li->max_latency = 0;
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li->min_latency = (u64)-1;
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li->latency_sum = 0;
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li->interrupt_cnt = 0;
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}
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static void start_timer(int timer, u64 interval)
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{
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union cvmx_ciu_timx timx;
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unsigned long flags;
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timx.u64 = 0;
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timx.s.one_shot = 1;
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timx.s.len = interval;
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raw_local_irq_save(flags);
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li.timer_start1 = read_c0_cvmcount();
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cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
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/* Read it back to force wait until register is written. */
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timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
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li.timer_start2 = read_c0_cvmcount();
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raw_local_irq_restore(flags);
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}
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static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id)
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{
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u64 last_latency;
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u64 last_int_cnt;
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if (reset_stats) {
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init_latency_info(&li, 0);
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reset_stats = false;
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} else {
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last_int_cnt = read_c0_cvmcount();
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last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval);
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li.interrupt_cnt++;
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li.latency_sum += last_latency;
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if (last_latency > li.max_latency)
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li.max_latency = last_latency;
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if (last_latency < li.min_latency)
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li.min_latency = last_latency;
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}
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start_timer(TIMER_NUM, li.io_interval);
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return IRQ_HANDLED;
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}
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static void disable_timer(int timer)
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{
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union cvmx_ciu_timx timx;
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timx.s.one_shot = 0;
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timx.s.len = 0;
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cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
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/* Read it back to force immediate write of timer register*/
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timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
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}
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static __init int oct_ilm_module_init(void)
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{
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int rc;
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int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM;
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init_debugfs();
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rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD,
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"oct_ilm", 0);
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if (rc) {
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WARN(1, "Could not acquire IRQ %d", irq);
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goto err_irq;
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}
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init_latency_info(&li, 1);
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start_timer(TIMER_NUM, li.io_interval);
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return 0;
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err_irq:
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debugfs_remove_recursive(dir);
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return rc;
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}
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static __exit void oct_ilm_module_exit(void)
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{
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disable_timer(TIMER_NUM);
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debugfs_remove_recursive(dir);
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free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0);
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}
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module_exit(oct_ilm_module_exit);
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module_init(oct_ilm_module_init);
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MODULE_AUTHOR("Venkat Subbiah, Cavium");
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MODULE_DESCRIPTION("Measures interrupt latency on Octeon chips.");
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MODULE_LICENSE("GPL");
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