143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#include <asm/addrspace.h>
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#include <asm/sync.h>
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static inline void __sync(void)
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{
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asm volatile(__SYNC(full, always) ::: "memory");
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}
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static inline void rmb(void)
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{
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asm volatile(__SYNC(rmb, always) ::: "memory");
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}
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#define rmb rmb
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static inline void wmb(void)
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{
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asm volatile(__SYNC(wmb, always) ::: "memory");
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}
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#define wmb wmb
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#define fast_mb() __sync()
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#define __fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"nop\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1) \
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: "memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define fast_iob() do { } while (0)
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#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
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# ifdef CONFIG_SGI_IP28
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# define fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"sync\n\t" \
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"lw $0,%0\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
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: "memory")
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# else
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# define fast_iob() \
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do { \
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__sync(); \
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__fast_iob(); \
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} while (0)
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# endif
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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#ifdef CONFIG_CPU_HAS_WB
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#include <asm/wbflush.h>
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#define mb() wbflush()
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#define iob() wbflush()
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#else /* !CONFIG_CPU_HAS_WB */
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#define mb() fast_mb()
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#define iob() fast_iob()
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#endif /* !CONFIG_CPU_HAS_WB */
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#if defined(CONFIG_WEAK_ORDERING)
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# define __smp_mb() __sync()
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# define __smp_rmb() rmb()
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# define __smp_wmb() wmb()
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#else
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# define __smp_mb() barrier()
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# define __smp_rmb() barrier()
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# define __smp_wmb() barrier()
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#endif
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/*
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* When LL/SC does imply order, it must also be a compiler barrier to avoid the
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* compiler from reordering where the CPU will not. When it does not imply
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* order, the compiler is also free to reorder across the LL/SC loop and
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* ordering will be done by smp_llsc_mb() and friends.
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*/
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#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
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# define __WEAK_LLSC_MB sync
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# define smp_llsc_mb() \
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__asm__ __volatile__(__stringify(__WEAK_LLSC_MB) : : :"memory")
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# define __LLSC_CLOBBER
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#else
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# define __WEAK_LLSC_MB
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# define smp_llsc_mb() do { } while (0)
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# define __LLSC_CLOBBER "memory"
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#endif
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define smp_mb__before_llsc() smp_wmb()
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#define __smp_mb__before_llsc() __smp_wmb()
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/* Cause previous writes to become visible on all CPUs as soon as possible */
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#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
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".set arch=octeon\n\t" \
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"syncw\n\t" \
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".set pop" : : : "memory")
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#else
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#define smp_mb__before_llsc() smp_llsc_mb()
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#define __smp_mb__before_llsc() smp_llsc_mb()
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#define nudge_writes() mb()
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#endif
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/*
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* In the Loongson3 LL/SC workaround case, all of our LL/SC loops already have
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* a completion barrier immediately preceding the LL instruction. Therefore we
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* can skip emitting a barrier from __smp_mb__before_atomic().
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*/
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#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
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# define __smp_mb__before_atomic()
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#else
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# define __smp_mb__before_atomic() __smp_mb__before_llsc()
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#endif
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#define __smp_mb__after_atomic() smp_llsc_mb()
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static inline void sync_ginv(void)
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{
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asm volatile(__SYNC(ginv, always));
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}
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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