220 lines
6.2 KiB
C
220 lines
6.2 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 Waldorf GMBH
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_CPU_INFO_H
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#define __ASM_CPU_INFO_H
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#include <linux/cache.h>
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#include <linux/types.h>
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#include <asm/mipsregs.h>
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/*
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* Descriptor for a cache
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*/
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struct cache_desc {
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unsigned int waysize; /* Bytes per way */
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unsigned short sets; /* Number of lines per set */
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unsigned char ways; /* Number of ways */
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unsigned char linesz; /* Size of line in bytes */
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unsigned char waybit; /* Bits to select in a cache set */
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unsigned char flags; /* Flags describing cache properties */
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};
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struct guest_info {
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unsigned long ases;
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unsigned long ases_dyn;
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unsigned long long options;
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unsigned long long options_dyn;
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int tlbsize;
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u8 conf;
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u8 kscratch_mask;
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};
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/*
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* Flag definitions
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*/
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#define MIPS_CACHE_NOT_PRESENT 0x00000001
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#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
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#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
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#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
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#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
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#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
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struct cpuinfo_mips {
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u64 asid_cache;
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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unsigned long asid_mask;
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#endif
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/*
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* Capability and feature descriptor structure for MIPS CPU
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*/
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unsigned long ases;
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unsigned long long options;
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unsigned int udelay_val;
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unsigned int processor_id;
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unsigned int fpu_id;
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unsigned int fpu_csr31;
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unsigned int fpu_msk31;
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unsigned int msa_id;
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unsigned int cputype;
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int isa_level;
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int tlbsize;
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int tlbsizevtlb;
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int tlbsizeftlbsets;
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int tlbsizeftlbways;
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struct cache_desc icache; /* Primary I-cache */
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struct cache_desc dcache; /* Primary D or combined I/D cache */
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struct cache_desc vcache; /* Victim cache, between pcache and scache */
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struct cache_desc scache; /* Secondary cache */
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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int srsets; /* Shadow register sets */
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int package;/* physical package number */
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unsigned int globalnumber;
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#ifdef CONFIG_64BIT
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int vmbits; /* Virtual memory size in bits */
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#endif
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void *data; /* Additional data */
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unsigned int watch_reg_count; /* Number that exist */
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unsigned int watch_reg_use_cnt; /* Usable by ptrace */
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#define NUM_WATCH_REGS 4
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u16 watch_reg_masks[NUM_WATCH_REGS];
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unsigned int kscratch_mask; /* Usable KScratch mask. */
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/*
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* Cache Coherency attribute for write-combine memory writes.
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* (shifted by _CACHE_SHIFT)
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*/
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unsigned int writecombine;
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/*
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* Simple counter to prevent enabling HTW in nested
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* htw_start/htw_stop calls
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*/
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unsigned int htw_seq;
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/* VZ & Guest features */
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struct guest_info guest;
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unsigned int gtoffset_mask;
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unsigned int guestid_mask;
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unsigned int guestid_cache;
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#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
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/* CPUCFG data for this CPU, synthesized at probe time.
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*
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* CPUCFG select 0 is PRId, 4 and above are unimplemented for now.
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* So the only stored values are for CPUCFG selects 1-3 inclusive.
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*/
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u32 loongson3_cpucfg_data[3];
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#endif
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} __attribute__((aligned(SMP_CACHE_BYTES)));
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extern struct cpuinfo_mips cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
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#define boot_cpu_data cpu_data[0]
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extern void cpu_probe(void);
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extern void cpu_report(void);
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extern const char *__cpu_name[];
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#define cpu_name_string() __cpu_name[raw_smp_processor_id()]
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struct seq_file;
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struct notifier_block;
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extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
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extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
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#define proc_cpuinfo_notifier(fn, pri) \
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({ \
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static struct notifier_block fn##_nb = { \
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.notifier_call = fn, \
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.priority = pri \
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}; \
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\
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register_proc_cpuinfo_notifier(&fn##_nb); \
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})
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struct proc_cpuinfo_notifier_args {
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struct seq_file *m;
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unsigned long n;
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};
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static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
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{
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/* Optimisation for systems where multiple clusters aren't used */
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if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
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return 0;
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return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
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MIPS_GLOBALNUMBER_CLUSTER_SHF;
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}
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static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
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{
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return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
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MIPS_GLOBALNUMBER_CORE_SHF;
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}
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static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
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{
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/* Optimisation for systems where VP(E)s aren't used */
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if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
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return 0;
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return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
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MIPS_GLOBALNUMBER_VP_SHF;
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}
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extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
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extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
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extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
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static inline bool cpus_are_siblings(int cpua, int cpub)
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{
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struct cpuinfo_mips *infoa = &cpu_data[cpua];
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struct cpuinfo_mips *infob = &cpu_data[cpub];
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unsigned int gnuma, gnumb;
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if (infoa->package != infob->package)
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return false;
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gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
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gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
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if (gnuma != gnumb)
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return false;
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return true;
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}
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static inline unsigned long cpu_asid_inc(void)
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{
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return 1 << CONFIG_MIPS_ASID_SHIFT;
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}
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static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo)
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{
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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return cpuinfo->asid_mask;
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#endif
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return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT;
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}
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static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo,
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unsigned long asid_mask)
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{
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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cpuinfo->asid_mask = asid_mask;
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#endif
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}
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#endif /* __ASM_CPU_INFO_H */
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