312 lines
7.4 KiB
C
312 lines
7.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
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*
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* Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 1999 - 2001 Kanoj Sarcar
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/sched.h>
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#include <asm/io.h>
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#include <asm/irq_cpu.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/agent.h>
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#include <asm/sn/arch.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/irq_alloc.h>
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struct hub_irq_data {
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u64 *irq_mask[2];
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cpuid_t cpu;
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};
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static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT);
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static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask);
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static inline int alloc_level(void)
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{
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int level;
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again:
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level = find_first_zero_bit(hub_irq_map, IP27_HUB_IRQ_COUNT);
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if (level >= IP27_HUB_IRQ_COUNT)
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return -ENOSPC;
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if (test_and_set_bit(level, hub_irq_map))
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goto again;
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return level;
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}
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static void enable_hub_irq(struct irq_data *d)
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{
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struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
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unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
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set_bit(d->hwirq, mask);
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__raw_writeq(mask[0], hd->irq_mask[0]);
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__raw_writeq(mask[1], hd->irq_mask[1]);
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}
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static void disable_hub_irq(struct irq_data *d)
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{
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struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
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unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
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clear_bit(d->hwirq, mask);
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__raw_writeq(mask[0], hd->irq_mask[0]);
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__raw_writeq(mask[1], hd->irq_mask[1]);
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}
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static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask)
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{
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nasid_t nasid;
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int cpu;
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cpu = cpumask_first_and(mask, cpu_online_mask);
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if (cpu >= nr_cpu_ids)
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cpu = cpumask_any(cpu_online_mask);
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nasid = cpu_to_node(cpu);
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hd->cpu = cpu;
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if (!cputoslice(cpu)) {
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hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A);
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hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A);
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} else {
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hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B);
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hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B);
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}
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}
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static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask,
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bool force)
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{
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struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
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if (!hd)
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return -EINVAL;
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if (irqd_is_started(d))
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disable_hub_irq(d);
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setup_hub_mask(hd, mask);
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if (irqd_is_started(d))
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enable_hub_irq(d);
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irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));
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return 0;
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}
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static struct irq_chip hub_irq_type = {
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.name = "HUB",
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.irq_mask = disable_hub_irq,
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.irq_unmask = enable_hub_irq,
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.irq_set_affinity = set_affinity_hub_irq,
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};
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static int hub_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct irq_alloc_info *info = arg;
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struct hub_irq_data *hd;
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struct hub_data *hub;
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struct irq_desc *desc;
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int swlevel;
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if (nr_irqs > 1 || !info)
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return -EINVAL;
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hd = kzalloc(sizeof(*hd), GFP_KERNEL);
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if (!hd)
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return -ENOMEM;
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swlevel = alloc_level();
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if (unlikely(swlevel < 0)) {
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kfree(hd);
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return -EAGAIN;
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}
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irq_domain_set_info(domain, virq, swlevel, &hub_irq_type, hd,
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handle_level_irq, NULL, NULL);
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/* use CPU connected to nearest hub */
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hub = hub_data(info->nasid);
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setup_hub_mask(hd, &hub->h_cpus);
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info->nasid = cpu_to_node(hd->cpu);
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/* Make sure it's not already pending when we connect it. */
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REMOTE_HUB_CLR_INTR(info->nasid, swlevel);
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desc = irq_to_desc(virq);
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desc->irq_common_data.node = info->nasid;
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cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus);
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return 0;
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}
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static void hub_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *irqd;
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if (nr_irqs > 1)
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return;
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irqd = irq_domain_get_irq_data(domain, virq);
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if (irqd && irqd->chip_data)
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kfree(irqd->chip_data);
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}
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static const struct irq_domain_ops hub_domain_ops = {
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.alloc = hub_domain_alloc,
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.free = hub_domain_free,
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};
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/*
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* This code is unnecessarily complex, because we do
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* intr enabling. Basically, once we grab the set of intrs we need
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* to service, we must mask _all_ these interrupts; firstly, to make
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* sure the same intr does not intr again, causing recursion that
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* can lead to stack overflow. Secondly, we can not just mask the
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* one intr we are do_IRQing, because the non-masked intrs in the
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* first set might intr again, causing multiple servicings of the
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* same intr. This effect is mostly seen for intercpu intrs.
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* Kanoj 05.13.00
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*/
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static void ip27_do_irq_mask0(struct irq_desc *desc)
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{
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cpuid_t cpu = smp_processor_id();
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unsigned long *mask = per_cpu(irq_enable_mask, cpu);
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struct irq_domain *domain;
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u64 pend0;
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int ret;
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/* copied from Irix intpend0() */
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pend0 = LOCAL_HUB_L(PI_INT_PEND0);
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pend0 &= mask[0]; /* Pick intrs we should look at */
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if (!pend0)
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return;
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#ifdef CONFIG_SMP
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if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
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scheduler_ipi();
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} else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
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scheduler_ipi();
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} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
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generic_smp_call_function_interrupt();
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} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
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generic_smp_call_function_interrupt();
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} else
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#endif
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{
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domain = irq_desc_get_handler_data(desc);
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ret = generic_handle_domain_irq(domain, __ffs(pend0));
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if (ret)
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spurious_interrupt();
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}
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LOCAL_HUB_L(PI_INT_PEND0);
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}
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static void ip27_do_irq_mask1(struct irq_desc *desc)
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{
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cpuid_t cpu = smp_processor_id();
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unsigned long *mask = per_cpu(irq_enable_mask, cpu);
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struct irq_domain *domain;
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u64 pend1;
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int ret;
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/* copied from Irix intpend0() */
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pend1 = LOCAL_HUB_L(PI_INT_PEND1);
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pend1 &= mask[1]; /* Pick intrs we should look at */
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if (!pend1)
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return;
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domain = irq_desc_get_handler_data(desc);
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ret = generic_handle_domain_irq(domain, __ffs(pend1) + 64);
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if (ret)
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spurious_interrupt();
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LOCAL_HUB_L(PI_INT_PEND1);
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}
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void install_ipi(void)
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{
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int cpu = smp_processor_id();
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unsigned long *mask = per_cpu(irq_enable_mask, cpu);
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int slice = LOCAL_HUB_L(PI_CPU_NUM);
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int resched, call;
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resched = CPU_RESCHED_A_IRQ + slice;
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set_bit(resched, mask);
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LOCAL_HUB_CLR_INTR(resched);
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call = CPU_CALL_A_IRQ + slice;
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set_bit(call, mask);
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LOCAL_HUB_CLR_INTR(call);
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if (slice == 0) {
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LOCAL_HUB_S(PI_INT_MASK0_A, mask[0]);
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LOCAL_HUB_S(PI_INT_MASK1_A, mask[1]);
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} else {
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LOCAL_HUB_S(PI_INT_MASK0_B, mask[0]);
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LOCAL_HUB_S(PI_INT_MASK1_B, mask[1]);
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}
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}
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void __init arch_init_irq(void)
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{
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struct irq_domain *domain;
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struct fwnode_handle *fn;
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int i;
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mips_cpu_irq_init();
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/*
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* Some interrupts are reserved by hardware or by software convention.
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* Mark these as reserved right away so they won't be used accidentally
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* later.
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*/
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for (i = 0; i <= CPU_CALL_B_IRQ; i++)
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set_bit(i, hub_irq_map);
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for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++)
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set_bit(i, hub_irq_map);
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fn = irq_domain_alloc_named_fwnode("HUB");
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WARN_ON(fn == NULL);
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if (!fn)
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return;
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domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT,
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&hub_domain_ops, NULL);
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WARN_ON(domain == NULL);
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if (!domain)
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return;
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irq_set_default_host(domain);
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irq_set_percpu_devid(IP27_HUB_PEND0_IRQ);
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irq_set_chained_handler_and_data(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0,
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domain);
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irq_set_percpu_devid(IP27_HUB_PEND1_IRQ);
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irq_set_chained_handler_and_data(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1,
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domain);
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}
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