581 lines
14 KiB
ArmAsm
581 lines
14 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2003-2013 Altera Corporation
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* All rights reserved.
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*/
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#include <linux/linkage.h>
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#include <asm/entry.h>
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.set noat
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.set nobreak
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/*
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* Explicitly allow the use of r1 (the assembler temporary register)
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* within this code. This register is normally reserved for the use of
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* the compiler.
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*/
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ENTRY(instruction_trap)
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ldw r1, PT_R1(sp) // Restore registers
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ldw r2, PT_R2(sp)
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ldw r3, PT_R3(sp)
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ldw r4, PT_R4(sp)
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ldw r5, PT_R5(sp)
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ldw r6, PT_R6(sp)
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ldw r7, PT_R7(sp)
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ldw r8, PT_R8(sp)
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ldw r9, PT_R9(sp)
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ldw r10, PT_R10(sp)
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ldw r11, PT_R11(sp)
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ldw r12, PT_R12(sp)
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ldw r13, PT_R13(sp)
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ldw r14, PT_R14(sp)
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ldw r15, PT_R15(sp)
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ldw ra, PT_RA(sp)
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ldw fp, PT_FP(sp)
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ldw gp, PT_GP(sp)
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ldw et, PT_ESTATUS(sp)
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wrctl estatus, et
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ldw ea, PT_EA(sp)
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ldw et, PT_SP(sp) /* backup sp in et */
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addi sp, sp, PT_REGS_SIZE
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/* INSTRUCTION EMULATION
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* ---------------------
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*
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* Nios II processors generate exceptions for unimplemented instructions.
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* The routines below emulate these instructions. Depending on the
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* processor core, the only instructions that might need to be emulated
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* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
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*
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* The emulations match the instructions, except for the following
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* limitations:
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*
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* 1) The emulation routines do not emulate the use of the exception
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* temporary register (et) as a source operand because the exception
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* handler already has modified it.
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*
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* 2) The routines do not emulate the use of the stack pointer (sp) or
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* the exception return address register (ea) as a destination because
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* modifying these registers crashes the exception handler or the
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* interrupted routine.
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*
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* Detailed Design
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* ---------------
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*
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* The emulation routines expect the contents of integer registers r0-r31
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* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
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* routines retrieve source operands from the stack and modify the
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* destination register's value on the stack prior to the end of the
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* exception handler. Then all registers except the destination register
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* are restored to their previous values.
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*
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* The instruction that causes the exception is found at address -4(ea).
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* The instruction's OP and OPX fields identify the operation to be
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* performed.
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*
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* One instruction, muli, is an I-type instruction that is identified by
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* an OP field of 0x24.
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*
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* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
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* 27 22 6 0 <-- LSB of field
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*
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* The remaining emulated instructions are R-type and have an OP field
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* of 0x3a. Their OPX fields identify them.
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*
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* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
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* 27 22 17 11 6 0 <-- LSB of field
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*
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*
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* Opcode Encoding. muli is identified by its OP value. Then OPX & 0x02
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* is used to differentiate between the division opcodes and the
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* remaining multiplication opcodes.
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*
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* Instruction OP OPX OPX & 0x02
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* ----------- ---- ---- ----------
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* muli 0x24
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* divu 0x3a 0x24 0
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* div 0x3a 0x25 0
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* mul 0x3a 0x27 != 0
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* mulxuu 0x3a 0x07 != 0
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* mulxsu 0x3a 0x17 != 0
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* mulxss 0x3a 0x1f != 0
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*/
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/*
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* Save everything on the stack to make it easy for the emulation
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* routines to retrieve the source register operands.
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*/
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addi sp, sp, -128
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stw zero, 0(sp) /* Save zero on stack to avoid special case for r0. */
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stw r1, 4(sp)
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stw r2, 8(sp)
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stw r3, 12(sp)
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stw r4, 16(sp)
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stw r5, 20(sp)
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stw r6, 24(sp)
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stw r7, 28(sp)
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stw r8, 32(sp)
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stw r9, 36(sp)
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stw r10, 40(sp)
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stw r11, 44(sp)
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stw r12, 48(sp)
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stw r13, 52(sp)
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stw r14, 56(sp)
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stw r15, 60(sp)
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stw r16, 64(sp)
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stw r17, 68(sp)
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stw r18, 72(sp)
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stw r19, 76(sp)
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stw r20, 80(sp)
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stw r21, 84(sp)
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stw r22, 88(sp)
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stw r23, 92(sp)
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/* Don't bother to save et. It's already been changed. */
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rdctl r5, estatus
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stw r5, 100(sp)
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stw gp, 104(sp)
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stw et, 108(sp) /* et contains previous sp value. */
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stw fp, 112(sp)
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stw ea, 116(sp)
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stw ra, 120(sp)
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/*
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* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
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* offsets to the stack pointer for access to the stored register values.
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*/
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ldw r2,-4(ea) /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
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roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
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roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
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roli r5, r4, 2 /* r5 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
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srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
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roli r6, r5, 5 /* r6 = XXXX,NNNNN,PPPPPP,AAAAA,BBBBB,CCCCC,XX */
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andi r2, r2, 0x3f /* r2 = 00000000000000000000000000,PPPPPP */
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andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,AAAAA,00 */
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andi r5, r5, 0x7c /* r5 = 0000000000000000000000000,BBBBB,00 */
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andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,CCCCC,00 */
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/* Now
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* r2 = OP
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* r3 = 4*A
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* r4 = IMM16 (sign extended)
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* r5 = 4*B
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* r6 = 4*C
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*/
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/*
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* Get the operands.
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*
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* It is necessary to check for muli because it uses an I-type
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* instruction format, while the other instructions are have an R-type
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* format.
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*
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* Prepare for either multiplication or division loop.
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* They both loop 32 times.
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*/
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movi r14, 32
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add r3, r3, sp /* r3 = address of A-operand. */
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ldw r3, 0(r3) /* r3 = A-operand. */
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movi r7, 0x24 /* muli opcode (I-type instruction format) */
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beq r2, r7, mul_immed /* muli doesn't use the B register as a source */
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add r5, r5, sp /* r5 = address of B-operand. */
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ldw r5, 0(r5) /* r5 = B-operand. */
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/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
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/* IMM16 not needed, align OPX portion */
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/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
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srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
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andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
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/* Now
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* r2 = OP
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* r3 = src1
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* r5 = src2
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* r4 = OPX (no longer can be muli)
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* r6 = 4*C
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*/
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/*
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* Multiply or Divide?
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*/
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andi r7, r4, 0x02 /* For R-type multiply instructions,
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OPX & 0x02 != 0 */
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bne r7, zero, multiply
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/* DIVISION
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*
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* Divide an unsigned dividend by an unsigned divisor using
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* a shift-and-subtract algorithm. The example below shows
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* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
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* single register to store both the dividend and the quotient,
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* allowing both values to be shifted with a single instruction.
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*
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* remainder dividend:quotient
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* --------- -----------------
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* initialize 00000000 00101011:
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* shift 00000000 0101011:_
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* remainder >= divisor? no 00000000 0101011:0
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* shift 00000000 101011:0_
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* remainder >= divisor? no 00000000 101011:00
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* shift 00000001 01011:00_
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* remainder >= divisor? no 00000001 01011:000
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* shift 00000010 1011:000_
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* remainder >= divisor? no 00000010 1011:0000
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* shift 00000101 011:0000_
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* remainder >= divisor? no 00000101 011:00000
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* shift 00001010 11:00000_
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* remainder >= divisor? yes 00001010 11:000001
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* remainder -= divisor - 00000111
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* ----------
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* 00000011 11:000001
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* shift 00000111 1:000001_
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* remainder >= divisor? yes 00000111 1:0000011
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* remainder -= divisor - 00000111
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* ----------
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* 00000000 1:0000011
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* shift 00000001 :0000011_
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* remainder >= divisor? no 00000001 :00000110
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*
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* The quotient is 00000110.
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*/
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divide:
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/*
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* Prepare for division by assuming the result
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* is unsigned, and storing its "sign" as 0.
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*/
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movi r17, 0
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/* Which division opcode? */
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xori r7, r4, 0x25 /* OPX of div */
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bne r7, zero, unsigned_division
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/*
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* OPX is div. Determine and store the sign of the quotient.
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* Then take the absolute value of both operands.
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*/
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xor r17, r3, r5 /* MSB contains sign of quotient */
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bge r3,zero,dividend_is_nonnegative
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sub r3, zero, r3 /* -r3 */
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dividend_is_nonnegative:
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bge r5, zero, divisor_is_nonnegative
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sub r5, zero, r5 /* -r5 */
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divisor_is_nonnegative:
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unsigned_division:
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/* Initialize the unsigned-division loop. */
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movi r13, 0 /* remainder = 0 */
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/* Now
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* r3 = dividend : quotient
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* r4 = 0x25 for div, 0x24 for divu
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* r5 = divisor
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* r13 = remainder
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* r14 = loop counter (already initialized to 32)
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* r17 = MSB contains sign of quotient
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*/
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/*
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* for (count = 32; count > 0; --count)
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* {
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*/
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divide_loop:
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/*
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* Division:
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*
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* (remainder:dividend:quotient) <<= 1;
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*/
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slli r13, r13, 1
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cmplt r7, r3, zero /* r7 = MSB of r3 */
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or r13, r13, r7
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slli r3, r3, 1
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/*
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* if (remainder >= divisor)
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* {
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* set LSB of quotient
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* remainder -= divisor;
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* }
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*/
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bltu r13, r5, div_skip
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ori r3, r3, 1
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sub r13, r13, r5
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div_skip:
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/*
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* }
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*/
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subi r14, r14, 1
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bne r14, zero, divide_loop
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/* Now
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* r3 = quotient
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* r4 = 0x25 for div, 0x24 for divu
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* r6 = 4*C
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* r17 = MSB contains sign of quotient
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*/
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/*
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* Conditionally negate signed quotient. If quotient is unsigned,
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* the sign already is initialized to 0.
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*/
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bge r17, zero, quotient_is_nonnegative
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sub r3, zero, r3 /* -r3 */
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quotient_is_nonnegative:
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/*
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* Final quotient is in r3.
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*/
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add r6, r6, sp
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stw r3, 0(r6) /* write quotient to stack */
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br restore_registers
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/* MULTIPLICATION
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*
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* A "product" is the number that one gets by summing a "multiplicand"
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* several times. The "multiplier" specifies the number of copies of the
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* multiplicand that are summed.
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*
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* Actual multiplication algorithms don't use repeated addition, however.
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* Shift-and-add algorithms get the same answer as repeated addition, and
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* they are faster. To compute the lower half of a product (pppp below)
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* one shifts the product left before adding in each of the partial
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* products (a * mmmm) through (d * mmmm).
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*
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* To compute the upper half of a product (PPPP below), one adds in the
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* partial products (d * mmmm) through (a * mmmm), each time following
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|
|
* the add by a right shift of the product.
|
||
|
|
*
|
||
|
|
* mmmm
|
||
|
|
* * abcd
|
||
|
|
* ------
|
||
|
|
* #### = d * mmmm
|
||
|
|
* #### = c * mmmm
|
||
|
|
* #### = b * mmmm
|
||
|
|
* #### = a * mmmm
|
||
|
|
* --------
|
||
|
|
* PPPPpppp
|
||
|
|
*
|
||
|
|
* The example above shows 4 partial products. Computing actual Nios II
|
||
|
|
* products requires 32 partials.
|
||
|
|
*
|
||
|
|
* It is possible to compute the result of mulxsu from the result of
|
||
|
|
* mulxuu because the only difference between the results of these two
|
||
|
|
* opcodes is the value of the partial product associated with the sign
|
||
|
|
* bit of rA.
|
||
|
|
*
|
||
|
|
* mulxsu = mulxuu - (rA < 0) ? rB : 0;
|
||
|
|
*
|
||
|
|
* It is possible to compute the result of mulxss from the result of
|
||
|
|
* mulxsu because the only difference between the results of these two
|
||
|
|
* opcodes is the value of the partial product associated with the sign
|
||
|
|
* bit of rB.
|
||
|
|
*
|
||
|
|
* mulxss = mulxsu - (rB < 0) ? rA : 0;
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
mul_immed:
|
||
|
|
/* Opcode is muli. Change it into mul for remainder of algorithm. */
|
||
|
|
mov r6, r5 /* Field B is dest register, not field C. */
|
||
|
|
mov r5, r4 /* Field IMM16 is src2, not field B. */
|
||
|
|
movi r4, 0x27 /* OPX of mul is 0x27 */
|
||
|
|
|
||
|
|
multiply:
|
||
|
|
/* Initialize the multiplication loop. */
|
||
|
|
movi r9, 0 /* mul_product = 0 */
|
||
|
|
movi r10, 0 /* mulxuu_product = 0 */
|
||
|
|
mov r11, r5 /* save original multiplier for mulxsu and mulxss */
|
||
|
|
mov r12, r5 /* mulxuu_multiplier (will be shifted) */
|
||
|
|
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
|
||
|
|
|
||
|
|
/* Now
|
||
|
|
* r3 = multiplicand
|
||
|
|
* r5 = mul_multiplier
|
||
|
|
* r6 = 4 * dest_register (used later as offset to sp)
|
||
|
|
* r7 = temp
|
||
|
|
* r9 = mul_product
|
||
|
|
* r10 = mulxuu_product
|
||
|
|
* r11 = original multiplier
|
||
|
|
* r12 = mulxuu_multiplier
|
||
|
|
* r14 = loop counter (already initialized)
|
||
|
|
* r16 = 1
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* for (count = 32; count > 0; --count)
|
||
|
|
* {
|
||
|
|
*/
|
||
|
|
multiply_loop:
|
||
|
|
|
||
|
|
/*
|
||
|
|
* mul_product <<= 1;
|
||
|
|
* lsb = multiplier & 1;
|
||
|
|
*/
|
||
|
|
slli r9, r9, 1
|
||
|
|
andi r7, r12, 1
|
||
|
|
|
||
|
|
/*
|
||
|
|
* if (lsb == 1)
|
||
|
|
* {
|
||
|
|
* mulxuu_product += multiplicand;
|
||
|
|
* }
|
||
|
|
*/
|
||
|
|
beq r7, zero, mulx_skip
|
||
|
|
add r10, r10, r3
|
||
|
|
cmpltu r7, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
|
||
|
|
ror r7, r7, r16 /* r7 = 0x80000000 on carry, or else 0x00000000 */
|
||
|
|
mulx_skip:
|
||
|
|
|
||
|
|
/*
|
||
|
|
* if (MSB of mul_multiplier == 1)
|
||
|
|
* {
|
||
|
|
* mul_product += multiplicand;
|
||
|
|
* }
|
||
|
|
*/
|
||
|
|
bge r5, zero, mul_skip
|
||
|
|
add r9, r9, r3
|
||
|
|
mul_skip:
|
||
|
|
|
||
|
|
/*
|
||
|
|
* mulxuu_product >>= 1; logical shift
|
||
|
|
* mul_multiplier <<= 1; done with MSB
|
||
|
|
* mulx_multiplier >>= 1; done with LSB
|
||
|
|
*/
|
||
|
|
srli r10, r10, 1
|
||
|
|
or r10, r10, r7 /* OR in the saved carry bit. */
|
||
|
|
slli r5, r5, 1
|
||
|
|
srli r12, r12, 1
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* }
|
||
|
|
*/
|
||
|
|
subi r14, r14, 1
|
||
|
|
bne r14, zero, multiply_loop
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Multiply emulation loop done.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Now
|
||
|
|
* r3 = multiplicand
|
||
|
|
* r4 = OPX
|
||
|
|
* r6 = 4 * dest_register (used later as offset to sp)
|
||
|
|
* r7 = temp
|
||
|
|
* r9 = mul_product
|
||
|
|
* r10 = mulxuu_product
|
||
|
|
* r11 = original multiplier
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/* Calculate address for result from 4 * dest_register */
|
||
|
|
add r6, r6, sp
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Select/compute the result based on OPX.
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/* OPX == mul? Then store. */
|
||
|
|
xori r7, r4, 0x27
|
||
|
|
beq r7, zero, store_product
|
||
|
|
|
||
|
|
/* It's one of the mulx.. opcodes. Move over the result. */
|
||
|
|
mov r9, r10
|
||
|
|
|
||
|
|
/* OPX == mulxuu? Then store. */
|
||
|
|
xori r7, r4, 0x07
|
||
|
|
beq r7, zero, store_product
|
||
|
|
|
||
|
|
/* Compute mulxsu
|
||
|
|
*
|
||
|
|
* mulxsu = mulxuu - (rA < 0) ? rB : 0;
|
||
|
|
*/
|
||
|
|
bge r3, zero, mulxsu_skip
|
||
|
|
sub r9, r9, r11
|
||
|
|
mulxsu_skip:
|
||
|
|
|
||
|
|
/* OPX == mulxsu? Then store. */
|
||
|
|
xori r7, r4, 0x17
|
||
|
|
beq r7, zero, store_product
|
||
|
|
|
||
|
|
/* Compute mulxss
|
||
|
|
*
|
||
|
|
* mulxss = mulxsu - (rB < 0) ? rA : 0;
|
||
|
|
*/
|
||
|
|
bge r11,zero,mulxss_skip
|
||
|
|
sub r9, r9, r3
|
||
|
|
mulxss_skip:
|
||
|
|
/* At this point, assume that OPX is mulxss, so store*/
|
||
|
|
|
||
|
|
|
||
|
|
store_product:
|
||
|
|
stw r9, 0(r6)
|
||
|
|
|
||
|
|
|
||
|
|
restore_registers:
|
||
|
|
/* No need to restore r0. */
|
||
|
|
ldw r5, 100(sp)
|
||
|
|
wrctl estatus, r5
|
||
|
|
|
||
|
|
ldw r1, 4(sp)
|
||
|
|
ldw r2, 8(sp)
|
||
|
|
ldw r3, 12(sp)
|
||
|
|
ldw r4, 16(sp)
|
||
|
|
ldw r5, 20(sp)
|
||
|
|
ldw r6, 24(sp)
|
||
|
|
ldw r7, 28(sp)
|
||
|
|
ldw r8, 32(sp)
|
||
|
|
ldw r9, 36(sp)
|
||
|
|
ldw r10, 40(sp)
|
||
|
|
ldw r11, 44(sp)
|
||
|
|
ldw r12, 48(sp)
|
||
|
|
ldw r13, 52(sp)
|
||
|
|
ldw r14, 56(sp)
|
||
|
|
ldw r15, 60(sp)
|
||
|
|
ldw r16, 64(sp)
|
||
|
|
ldw r17, 68(sp)
|
||
|
|
ldw r18, 72(sp)
|
||
|
|
ldw r19, 76(sp)
|
||
|
|
ldw r20, 80(sp)
|
||
|
|
ldw r21, 84(sp)
|
||
|
|
ldw r22, 88(sp)
|
||
|
|
ldw r23, 92(sp)
|
||
|
|
/* Does not need to restore et */
|
||
|
|
ldw gp, 104(sp)
|
||
|
|
|
||
|
|
ldw fp, 112(sp)
|
||
|
|
ldw ea, 116(sp)
|
||
|
|
ldw ra, 120(sp)
|
||
|
|
ldw sp, 108(sp) /* last restore sp */
|
||
|
|
eret
|
||
|
|
|
||
|
|
.set at
|
||
|
|
.set break
|