205 lines
5.0 KiB
C
205 lines
5.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* ICSWX api
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*
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* Copyright (C) 2015 IBM Corp.
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*
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* This provides the Initiate Coprocessor Store Word Indexed (ICSWX)
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* instruction. This instruction is used to communicate with PowerPC
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* coprocessors. This also provides definitions of the structures used
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* to communicate with the coprocessor.
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*
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* The RFC02130: Coprocessor Architecture document is the reference for
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* everything in this file unless otherwise noted.
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*/
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#ifndef _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_
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#define _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_
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#include <asm/ppc-opcode.h> /* for PPC_ICSWX */
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/* Chapter 6.5.8 Coprocessor-Completion Block (CCB) */
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#define CCB_VALUE (0x3fffffffffffffff)
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#define CCB_ADDRESS (0xfffffffffffffff8)
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#define CCB_CM (0x0000000000000007)
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#define CCB_CM0 (0x0000000000000004)
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#define CCB_CM12 (0x0000000000000003)
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#define CCB_CM0_ALL_COMPLETIONS (0x0)
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#define CCB_CM0_LAST_IN_CHAIN (0x4)
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#define CCB_CM12_STORE (0x0)
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#define CCB_CM12_INTERRUPT (0x1)
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#define CCB_SIZE (0x10)
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#define CCB_ALIGN CCB_SIZE
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struct coprocessor_completion_block {
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__be64 value;
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__be64 address;
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} __packed __aligned(CCB_ALIGN);
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/* Chapter 6.5.7 Coprocessor-Status Block (CSB) */
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#define CSB_V (0x80)
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#define CSB_F (0x04)
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#define CSB_CH (0x03)
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#define CSB_CE_INCOMPLETE (0x80)
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#define CSB_CE_TERMINATION (0x40)
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#define CSB_CE_TPBC (0x20)
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#define CSB_CC_SUCCESS (0)
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#define CSB_CC_INVALID_ALIGN (1)
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#define CSB_CC_OPERAND_OVERLAP (2)
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#define CSB_CC_DATA_LENGTH (3)
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#define CSB_CC_TRANSLATION (5)
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#define CSB_CC_PROTECTION (6)
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#define CSB_CC_RD_EXTERNAL (7)
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#define CSB_CC_INVALID_OPERAND (8)
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#define CSB_CC_PRIVILEGE (9)
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#define CSB_CC_INTERNAL (10)
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#define CSB_CC_WR_EXTERNAL (12)
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#define CSB_CC_NOSPC (13)
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#define CSB_CC_EXCESSIVE_DDE (14)
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#define CSB_CC_WR_TRANSLATION (15)
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#define CSB_CC_WR_PROTECTION (16)
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#define CSB_CC_UNKNOWN_CODE (17)
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#define CSB_CC_ABORT (18)
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#define CSB_CC_EXCEED_BYTE_COUNT (19) /* P9 or later */
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#define CSB_CC_TRANSPORT (20)
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#define CSB_CC_INVALID_CRB (21) /* P9 or later */
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#define CSB_CC_INVALID_DDE (30) /* P9 or later */
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#define CSB_CC_SEGMENTED_DDL (31)
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#define CSB_CC_PROGRESS_POINT (32)
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#define CSB_CC_DDE_OVERFLOW (33)
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#define CSB_CC_SESSION (34)
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#define CSB_CC_PROVISION (36)
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#define CSB_CC_CHAIN (37)
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#define CSB_CC_SEQUENCE (38)
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#define CSB_CC_HW (39)
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/* P9 DD2 NX Workbook 3.2 (Table 4-36): Address translation fault */
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#define CSB_CC_FAULT_ADDRESS (250)
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#define CSB_SIZE (0x10)
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#define CSB_ALIGN CSB_SIZE
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struct coprocessor_status_block {
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u8 flags;
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u8 cs;
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u8 cc;
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u8 ce;
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__be32 count;
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__be64 address;
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} __packed __aligned(CSB_ALIGN);
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/* Chapter 6.5.10 Data-Descriptor List (DDL)
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* each list contains one or more Data-Descriptor Entries (DDE)
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*/
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#define DDE_P (0x8000)
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#define DDE_SIZE (0x10)
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#define DDE_ALIGN DDE_SIZE
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struct data_descriptor_entry {
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__be16 flags;
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u8 count;
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u8 index;
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__be32 length;
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__be64 address;
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} __packed __aligned(DDE_ALIGN);
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/* 4.3.2 NX-stamped Fault CRB */
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#define NX_STAMP_ALIGN (0x10)
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struct nx_fault_stamp {
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__be64 fault_storage_addr;
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__be16 reserved;
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__u8 flags;
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__u8 fault_status;
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__be32 pswid;
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} __packed __aligned(NX_STAMP_ALIGN);
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/* Chapter 6.5.2 Coprocessor-Request Block (CRB) */
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#define CRB_SIZE (0x80)
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#define CRB_ALIGN (0x100) /* Errata: requires 256 alignment */
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/* Coprocessor Status Block field
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* ADDRESS address of CSB
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* C CCB is valid
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* AT 0 = addrs are virtual, 1 = addrs are phys
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* M enable perf monitor
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*/
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#define CRB_CSB_ADDRESS (0xfffffffffffffff0)
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#define CRB_CSB_C (0x0000000000000008)
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#define CRB_CSB_AT (0x0000000000000002)
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#define CRB_CSB_M (0x0000000000000001)
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struct coprocessor_request_block {
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__be32 ccw;
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__be32 flags;
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__be64 csb_addr;
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struct data_descriptor_entry source;
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struct data_descriptor_entry target;
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struct coprocessor_completion_block ccb;
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union {
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struct nx_fault_stamp nx;
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u8 reserved[16];
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} stamp;
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u8 reserved[32];
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struct coprocessor_status_block csb;
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} __aligned(128);
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/* RFC02167 Initiate Coprocessor Instructions document
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* Chapter 8.2.1.1.1 RS
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* Chapter 8.2.3 Coprocessor Directive
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* Chapter 8.2.4 Execution
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*
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* The CCW must be converted to BE before passing to icswx()
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*/
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#define CCW_PS (0xff000000)
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#define CCW_CT (0x00ff0000)
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#define CCW_CD (0x0000ffff)
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#define CCW_CL (0x0000c000)
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/* RFC02167 Initiate Coprocessor Instructions document
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* Chapter 8.2.1 Initiate Coprocessor Store Word Indexed (ICSWX)
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* Chapter 8.2.4.1 Condition Register 0
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*/
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#define ICSWX_INITIATED (0x8)
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#define ICSWX_BUSY (0x4)
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#define ICSWX_REJECTED (0x2)
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#define ICSWX_XERS0 (0x1) /* undefined or set from XERSO. */
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static inline int icswx(__be32 ccw, struct coprocessor_request_block *crb)
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{
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__be64 ccw_reg = ccw;
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u32 cr;
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/* NB: the same structures are used by VAS-NX */
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BUILD_BUG_ON(sizeof(*crb) != 128);
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__asm__ __volatile__(
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PPC_ICSWX(%1,0,%2) "\n"
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"mfcr %0\n"
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: "=r" (cr)
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: "r" (ccw_reg), "r" (crb)
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: "cr0", "memory");
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return (int)((cr >> 28) & 0xf);
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}
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#endif /* _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_ */
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