293 lines
8.2 KiB
C
293 lines
8.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
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#define _ASM_POWERPC_NOHASH_PGTABLE_H
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#if defined(CONFIG_PPC64)
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#include <asm/nohash/64/pgtable.h>
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#else
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#include <asm/nohash/32/pgtable.h>
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#endif
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/* Permission masks used for kernel mappings */
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#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
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#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE)
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#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE | _PAGE_GUARDED)
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#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
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#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
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#ifndef __ASSEMBLY__
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/* Generic accessors to PTE bits */
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#ifndef pte_write
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static inline int pte_write(pte_t pte)
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{
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return pte_val(pte) & _PAGE_RW;
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}
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#endif
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static inline int pte_read(pte_t pte) { return 1; }
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
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static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
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static inline bool pte_hashpte(pte_t pte) { return false; }
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static inline bool pte_ci(pte_t pte) { return pte_val(pte) & _PAGE_NO_CACHE; }
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static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
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#ifdef CONFIG_NUMA_BALANCING
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/*
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* These work without NUMA balancing but the kernel does not care. See the
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* comment in include/linux/pgtable.h . On powerpc, this will only
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* work for user pages and always return true for kernel pages.
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*/
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static inline int pte_protnone(pte_t pte)
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{
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return pte_present(pte) && !pte_user(pte);
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}
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static inline int pmd_protnone(pmd_t pmd)
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{
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return pte_protnone(pmd_pte(pmd));
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}
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#endif /* CONFIG_NUMA_BALANCING */
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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static inline bool pte_hw_valid(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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/*
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* Don't just check for any non zero bits in __PAGE_USER, since for book3e
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* and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in
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* _PAGE_USER. Need to explicitly match _PAGE_BAP_UR bit in that case too.
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*/
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#ifndef pte_user
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static inline bool pte_user(pte_t pte)
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{
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return (pte_val(pte) & _PAGE_USER) == _PAGE_USER;
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}
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#endif
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/*
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* We only find page table entry in the last level
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* Hence no need for other accessors
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*/
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#define pte_access_permitted pte_access_permitted
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static inline bool pte_access_permitted(pte_t pte, bool write)
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{
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/*
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* A read-only access is controlled by _PAGE_USER bit.
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* We have _PAGE_READ set for WRITE and EXECUTE
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*/
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if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
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return false;
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if (write && !pte_write(pte))
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return false;
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return true;
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}
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/* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* Even if PTEs can be unsigned long long, a PFN is always an unsigned
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* long for now.
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*/
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
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return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
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pgprot_val(pgprot)); }
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static inline unsigned long pte_pfn(pte_t pte) {
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return pte_val(pte) >> PTE_RPN_SHIFT; }
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/* Generic modifiers for PTE bits */
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static inline pte_t pte_exprotect(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_EXEC);
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_DIRTY);
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
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}
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static inline pte_t pte_mkspecial(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SPECIAL);
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}
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#ifndef pte_mkhuge
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static inline pte_t pte_mkhuge(pte_t pte)
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{
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return __pte(pte_val(pte));
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}
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#endif
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#ifndef pte_mkprivileged
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static inline pte_t pte_mkprivileged(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_USER);
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}
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#endif
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#ifndef pte_mkuser
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static inline pte_t pte_mkuser(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_USER);
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}
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#endif
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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static inline int pte_swp_exclusive(pte_t pte)
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{
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return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
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}
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static inline pte_t pte_swp_mkexclusive(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE);
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}
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static inline pte_t pte_swp_clear_exclusive(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE);
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}
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/* Insert a PTE, top-level function is out of line. It uses an inline
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* low level function in the respective pgtable-* files
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*/
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extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte);
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
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* an horrible mess that I'm not going to try to clean up now but
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* I'm keeping it in one place rather than spread around
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*/
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static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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/* Second case is 32-bit with 64-bit PTE. In this case, we
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* can just store as long as we do the two halves in the right order
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* with a barrier in between.
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* In the percpu case, we also fallback to the simple update
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*/
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if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) {
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__asm__ __volatile__("\
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stw%X0 %2,%0\n\
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mbar\n\
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stw%X1 %L2,%1"
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: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
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: "r" (pte) : "memory");
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return;
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}
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/* Anything else just stores the PTE normally. That covers all 64-bit
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* cases, and 32-bit non-hash with 32-bit PTEs.
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*/
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#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
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ptep->pte3 = ptep->pte2 = ptep->pte1 = ptep->pte = pte_val(pte);
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#else
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*ptep = pte;
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#endif
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/*
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* With hardware tablewalk, a sync is needed to ensure that
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* subsequent accesses see the PTE we just wrote. Unlike userspace
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* mappings, we can't tolerate spurious faults, so make sure
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* the new PTE will be seen the first time.
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*/
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if (IS_ENABLED(CONFIG_PPC_BOOK3E_64) && is_kernel_addr(addr))
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mb();
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}
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep, pte_t entry, int dirty);
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU)
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#define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE | _PAGE_GUARDED))
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#define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE))
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#define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT))
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#if _PAGE_WRITETHRU != 0
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#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT | _PAGE_WRITETHRU))
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#else
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#define pgprot_cached_wthru(prot) pgprot_noncached(prot)
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#endif
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#define pgprot_cached_noncoherent(prot) \
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(__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
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#define pgprot_writecombine pgprot_noncached_wc
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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#ifdef CONFIG_HUGETLB_PAGE
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static inline int hugepd_ok(hugepd_t hpd)
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{
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#ifdef CONFIG_PPC_8xx
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return ((hpd_val(hpd) & _PMD_PAGE_MASK) == _PMD_PAGE_8M);
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#else
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/* We clear the top bit to indicate hugepd */
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return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0);
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#endif
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}
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static inline int pmd_huge(pmd_t pmd)
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{
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return 0;
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}
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static inline int pud_huge(pud_t pud)
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{
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return 0;
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}
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#define is_hugepd(hpd) (hugepd_ok(hpd))
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#endif
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/*
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* This gets called at the end of handling a page fault, when
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* the kernel has put a new PTE into the page table for the process.
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* We use it to ensure coherency between the i-cache and d-cache
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* for the page which has just been mapped in.
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*/
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#if defined(CONFIG_PPC_E500) && defined(CONFIG_HUGETLB_PAGE)
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep);
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#else
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static inline
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) {}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif
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