439 lines
13 KiB
C
439 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_ATOMIC_H
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#define _ASM_RISCV_ATOMIC_H
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#ifdef CONFIG_GENERIC_ATOMIC64
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# include <asm-generic/atomic64.h>
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#else
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# if (__riscv_xlen < 64)
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# error "64-bit atomics require XLEN to be at least 64"
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# endif
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#endif
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#define __atomic_acquire_fence() \
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__asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory")
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#define __atomic_release_fence() \
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__asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory");
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static __always_inline int arch_atomic_read(const atomic_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void arch_atomic_set(atomic_t *v, int i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC64_INIT(i) { (i) }
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static __always_inline s64 arch_atomic64_read(const atomic64_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void arch_atomic64_set(atomic64_t *v, s64 i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#endif
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/*
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* First, the atomic ops that have no ordering constraints and therefor don't
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* have the AQ or RL bits set. These don't return anything, so there's only
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* one version to worry about.
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*/
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#define ATOMIC_OP(op, asm_op, I, asm_type, c_type, prefix) \
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static __always_inline \
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void arch_atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
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{ \
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__asm__ __volatile__ ( \
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" amo" #asm_op "." #asm_type " zero, %1, %0" \
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: "+A" (v->counter) \
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: "r" (I) \
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: "memory"); \
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} \
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_OP (op, asm_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_OP (op, asm_op, I, w, int, ) \
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ATOMIC_OP (op, asm_op, I, d, s64, 64)
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#endif
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ATOMIC_OPS(add, add, i)
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ATOMIC_OPS(sub, add, -i)
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ATOMIC_OPS(and, and, i)
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ATOMIC_OPS( or, or, i)
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ATOMIC_OPS(xor, xor, i)
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#undef ATOMIC_OP
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#undef ATOMIC_OPS
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/*
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* Atomic ops that have ordered, relaxed, acquire, and release variants.
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* There's two flavors of these: the arithmatic ops have both fetch and return
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* versions, while the logical ops only have fetch versions.
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*/
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#define ATOMIC_FETCH_OP(op, asm_op, I, asm_type, c_type, prefix) \
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static __always_inline \
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c_type arch_atomic##prefix##_fetch_##op##_relaxed(c_type i, \
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atomic##prefix##_t *v) \
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{ \
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register c_type ret; \
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__asm__ __volatile__ ( \
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" amo" #asm_op "." #asm_type " %1, %2, %0" \
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: "+A" (v->counter), "=r" (ret) \
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: "r" (I) \
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: "memory"); \
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return ret; \
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} \
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static __always_inline \
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c_type arch_atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \
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{ \
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register c_type ret; \
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__asm__ __volatile__ ( \
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" amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \
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: "+A" (v->counter), "=r" (ret) \
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: "r" (I) \
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: "memory"); \
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return ret; \
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}
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#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_type, c_type, prefix) \
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static __always_inline \
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c_type arch_atomic##prefix##_##op##_return_relaxed(c_type i, \
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atomic##prefix##_t *v) \
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{ \
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return arch_atomic##prefix##_fetch_##op##_relaxed(i, v) c_op I; \
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} \
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static __always_inline \
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c_type arch_atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \
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{ \
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return arch_atomic##prefix##_fetch_##op(i, v) c_op I; \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) \
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ATOMIC_FETCH_OP( op, asm_op, I, d, s64, 64) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, d, s64, 64)
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#endif
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ATOMIC_OPS(add, add, +, i)
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ATOMIC_OPS(sub, add, +, -i)
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#define arch_atomic_add_return arch_atomic_add_return
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#define arch_atomic_sub_return arch_atomic_sub_return
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#define arch_atomic_fetch_add arch_atomic_fetch_add
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#define arch_atomic_fetch_sub arch_atomic_fetch_sub
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
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#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
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#define arch_atomic64_add_return arch_atomic64_add_return
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#define arch_atomic64_sub_return arch_atomic64_sub_return
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#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
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#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
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#define arch_atomic64_fetch_add arch_atomic64_fetch_add
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#define arch_atomic64_fetch_sub arch_atomic64_fetch_sub
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#endif
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#undef ATOMIC_OPS
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) \
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ATOMIC_FETCH_OP(op, asm_op, I, d, s64, 64)
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#endif
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ATOMIC_OPS(and, and, i)
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ATOMIC_OPS( or, or, i)
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ATOMIC_OPS(xor, xor, i)
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#define arch_atomic_fetch_and arch_atomic_fetch_and
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#define arch_atomic_fetch_or arch_atomic_fetch_or
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#define arch_atomic_fetch_xor arch_atomic_fetch_xor
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
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#define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
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#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
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#define arch_atomic64_fetch_and arch_atomic64_fetch_and
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#define arch_atomic64_fetch_or arch_atomic64_fetch_or
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#define arch_atomic64_fetch_xor arch_atomic64_fetch_xor
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#endif
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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/* This is required to provide a full barrier on success. */
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static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int prev, rc;
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__asm__ __volatile__ (
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"0: lr.w %[p], %[c]\n"
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" beq %[p], %[u], 1f\n"
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" add %[rc], %[p], %[a]\n"
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" sc.w.rl %[rc], %[rc], %[c]\n"
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" bnez %[rc], 0b\n"
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" fence rw, rw\n"
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"1:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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#define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
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{
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s64 prev;
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long rc;
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__asm__ __volatile__ (
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"0: lr.d %[p], %[c]\n"
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" beq %[p], %[u], 1f\n"
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" add %[rc], %[p], %[a]\n"
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" sc.d.rl %[rc], %[rc], %[c]\n"
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" bnez %[rc], 0b\n"
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" fence rw, rw\n"
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"1:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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#define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless
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#endif
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/*
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* atomic_{cmp,}xchg is required to have exactly the same ordering semantics as
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* {cmp,}xchg and the operations that return, so they need a full barrier.
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*/
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#define ATOMIC_OP(c_t, prefix, size) \
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static __always_inline \
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c_t arch_atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \
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{ \
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return __xchg_relaxed(&(v->counter), n, size); \
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} \
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static __always_inline \
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c_t arch_atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \
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{ \
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return __xchg_acquire(&(v->counter), n, size); \
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} \
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static __always_inline \
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c_t arch_atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \
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{ \
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return __xchg_release(&(v->counter), n, size); \
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} \
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static __always_inline \
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c_t arch_atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \
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{ \
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return __xchg(&(v->counter), n, size); \
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} \
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static __always_inline \
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c_t arch_atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \
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c_t o, c_t n) \
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{ \
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return __cmpxchg_relaxed(&(v->counter), o, n, size); \
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} \
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static __always_inline \
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c_t arch_atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \
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c_t o, c_t n) \
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{ \
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return __cmpxchg_acquire(&(v->counter), o, n, size); \
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} \
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static __always_inline \
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c_t arch_atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \
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c_t o, c_t n) \
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{ \
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return __cmpxchg_release(&(v->counter), o, n, size); \
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} \
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static __always_inline \
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c_t arch_atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \
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{ \
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return __cmpxchg(&(v->counter), o, n, size); \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS() \
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ATOMIC_OP(int, , 4)
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#else
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#define ATOMIC_OPS() \
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ATOMIC_OP(int, , 4) \
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ATOMIC_OP(s64, 64, 8)
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#endif
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ATOMIC_OPS()
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#define arch_atomic_xchg_relaxed arch_atomic_xchg_relaxed
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#define arch_atomic_xchg_acquire arch_atomic_xchg_acquire
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#define arch_atomic_xchg_release arch_atomic_xchg_release
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#define arch_atomic_xchg arch_atomic_xchg
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#define arch_atomic_cmpxchg_relaxed arch_atomic_cmpxchg_relaxed
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#define arch_atomic_cmpxchg_acquire arch_atomic_cmpxchg_acquire
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#define arch_atomic_cmpxchg_release arch_atomic_cmpxchg_release
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#define arch_atomic_cmpxchg arch_atomic_cmpxchg
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#undef ATOMIC_OPS
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#undef ATOMIC_OP
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static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v)
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{
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int prev, rc;
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__asm__ __volatile__ (
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"0: lr.w %[p], %[c]\n"
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" bltz %[p], 1f\n"
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" addi %[rc], %[p], 1\n"
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" sc.w.rl %[rc], %[rc], %[c]\n"
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" bnez %[rc], 0b\n"
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" fence rw, rw\n"
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"1:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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|
|
:
|
||
|
|
: "memory");
|
||
|
|
return !(prev < 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define arch_atomic_inc_unless_negative arch_atomic_inc_unless_negative
|
||
|
|
|
||
|
|
static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v)
|
||
|
|
{
|
||
|
|
int prev, rc;
|
||
|
|
|
||
|
|
__asm__ __volatile__ (
|
||
|
|
"0: lr.w %[p], %[c]\n"
|
||
|
|
" bgtz %[p], 1f\n"
|
||
|
|
" addi %[rc], %[p], -1\n"
|
||
|
|
" sc.w.rl %[rc], %[rc], %[c]\n"
|
||
|
|
" bnez %[rc], 0b\n"
|
||
|
|
" fence rw, rw\n"
|
||
|
|
"1:\n"
|
||
|
|
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
|
||
|
|
:
|
||
|
|
: "memory");
|
||
|
|
return !(prev > 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define arch_atomic_dec_unless_positive arch_atomic_dec_unless_positive
|
||
|
|
|
||
|
|
static __always_inline int arch_atomic_dec_if_positive(atomic_t *v)
|
||
|
|
{
|
||
|
|
int prev, rc;
|
||
|
|
|
||
|
|
__asm__ __volatile__ (
|
||
|
|
"0: lr.w %[p], %[c]\n"
|
||
|
|
" addi %[rc], %[p], -1\n"
|
||
|
|
" bltz %[rc], 1f\n"
|
||
|
|
" sc.w.rl %[rc], %[rc], %[c]\n"
|
||
|
|
" bnez %[rc], 0b\n"
|
||
|
|
" fence rw, rw\n"
|
||
|
|
"1:\n"
|
||
|
|
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
|
||
|
|
:
|
||
|
|
: "memory");
|
||
|
|
return prev - 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define arch_atomic_dec_if_positive arch_atomic_dec_if_positive
|
||
|
|
|
||
|
|
#ifndef CONFIG_GENERIC_ATOMIC64
|
||
|
|
static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 prev;
|
||
|
|
long rc;
|
||
|
|
|
||
|
|
__asm__ __volatile__ (
|
||
|
|
"0: lr.d %[p], %[c]\n"
|
||
|
|
" bltz %[p], 1f\n"
|
||
|
|
" addi %[rc], %[p], 1\n"
|
||
|
|
" sc.d.rl %[rc], %[rc], %[c]\n"
|
||
|
|
" bnez %[rc], 0b\n"
|
||
|
|
" fence rw, rw\n"
|
||
|
|
"1:\n"
|
||
|
|
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
|
||
|
|
:
|
||
|
|
: "memory");
|
||
|
|
return !(prev < 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define arch_atomic64_inc_unless_negative arch_atomic64_inc_unless_negative
|
||
|
|
|
||
|
|
static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 prev;
|
||
|
|
long rc;
|
||
|
|
|
||
|
|
__asm__ __volatile__ (
|
||
|
|
"0: lr.d %[p], %[c]\n"
|
||
|
|
" bgtz %[p], 1f\n"
|
||
|
|
" addi %[rc], %[p], -1\n"
|
||
|
|
" sc.d.rl %[rc], %[rc], %[c]\n"
|
||
|
|
" bnez %[rc], 0b\n"
|
||
|
|
" fence rw, rw\n"
|
||
|
|
"1:\n"
|
||
|
|
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
|
||
|
|
:
|
||
|
|
: "memory");
|
||
|
|
return !(prev > 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define arch_atomic64_dec_unless_positive arch_atomic64_dec_unless_positive
|
||
|
|
|
||
|
|
static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 prev;
|
||
|
|
long rc;
|
||
|
|
|
||
|
|
__asm__ __volatile__ (
|
||
|
|
"0: lr.d %[p], %[c]\n"
|
||
|
|
" addi %[rc], %[p], -1\n"
|
||
|
|
" bltz %[rc], 1f\n"
|
||
|
|
" sc.d.rl %[rc], %[rc], %[c]\n"
|
||
|
|
" bnez %[rc], 0b\n"
|
||
|
|
" fence rw, rw\n"
|
||
|
|
"1:\n"
|
||
|
|
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
|
||
|
|
:
|
||
|
|
: "memory");
|
||
|
|
return prev - 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _ASM_RISCV_ATOMIC_H */
|