84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas Solutions Highlander R7785RP Support.
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*
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* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
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* Copyright (C) 2006 - 2008 Paul Mundt
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* Copyright (C) 2007 Magnus Damm
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/highlander.h>
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enum {
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UNUSED = 0,
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/* FPGA specific interrupt sources */
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CF, /* Compact Flash */
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SMBUS, /* SMBUS */
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TP, /* Touch panel */
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RTC, /* RTC Alarm */
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TH_ALERT, /* Temperature sensor */
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AX88796, /* Ethernet controller */
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/* external bus connector */
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EXT0, EXT1, EXT2, EXT3, EXT4, EXT5, EXT6, EXT7,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(CF, IRQ_CF),
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INTC_IRQ(SMBUS, IRQ_SMBUS),
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INTC_IRQ(TP, IRQ_TP),
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INTC_IRQ(RTC, IRQ_RTC),
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INTC_IRQ(TH_ALERT, IRQ_TH_ALERT),
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INTC_IRQ(EXT0, IRQ_EXT0), INTC_IRQ(EXT1, IRQ_EXT1),
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INTC_IRQ(EXT2, IRQ_EXT2), INTC_IRQ(EXT3, IRQ_EXT3),
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INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
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INTC_IRQ(EXT6, IRQ_EXT6), INTC_IRQ(EXT7, IRQ_EXT7),
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INTC_IRQ(AX88796, IRQ_AX88796),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xa4000010, 0, 16, /* IRLMCR1 */
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{ 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
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RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
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{ 0xa4000012, 0, 16, /* IRLMCR2 */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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EXT7, EXT6, EXT5, EXT4, EXT3, EXT2, EXT1, EXT0 } },
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};
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static unsigned char irl2irq[HL_NR_IRL] __initdata = {
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0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
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IRQ_EXT6, IRQ_EXT7, IRQ_SMBUS, IRQ_TP,
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IRQ_RTC, IRQ_TH_ALERT, IRQ_AX88796, IRQ_EXT0,
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IRQ_EXT1, IRQ_EXT2, IRQ_EXT3,
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};
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static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
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NULL, mask_registers, NULL, NULL);
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unsigned char * __init highlander_plat_irq_setup(void)
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{
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if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
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return NULL;
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printk(KERN_INFO "Using r7785rp interrupt controller.\n");
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__raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
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/* Setup the FPGA IRL */
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__raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
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__raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
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__raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
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__raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
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__raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
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__raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
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register_intc_controller(&intc_desc);
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return irl2irq;
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}
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