82 lines
4.4 KiB
C
82 lines
4.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* fhc.h: FHC and Clock board register definitions.
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*
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* Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
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*/
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#ifndef _SPARC64_FHC_H
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#define _SPARC64_FHC_H
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/* Clock board register offsets. */
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#define CLOCK_CTRL 0x00UL /* Main control */
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#define CLOCK_STAT1 0x10UL /* Status one */
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#define CLOCK_STAT2 0x20UL /* Status two */
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#define CLOCK_PWRSTAT 0x30UL /* Power status */
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#define CLOCK_PWRPRES 0x40UL /* Power presence */
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#define CLOCK_TEMP 0x50UL /* Temperature */
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#define CLOCK_IRQDIAG 0x60UL /* IRQ diagnostics */
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#define CLOCK_PWRSTAT2 0x70UL /* Power status two */
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#define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */
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#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
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#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
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/* Firehose controller register offsets */
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#define FHC_PREGS_ID 0x00UL /* FHC ID */
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#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */
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#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */
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#define FHC_ID_MANUF 0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
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#define FHC_ID_RESV 0x00000001 /* Read as one */
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#define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
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#define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
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#define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
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#define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
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#define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
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#define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
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#define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
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#define FHC_RCS_CFATAL 0x02000000 /* Centerplane Fatal Error signalled */
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#define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
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#define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
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#define FHC_CONTROL_ICS 0x00100000 /* Ignore Centerplane Signals */
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#define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
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#define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */
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#define FHC_CONTROL_SLINE 0x00010000 /* Firmware Synchronization Line */
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#define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
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#define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
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#define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
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#define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
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#define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
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#define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */
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#define FHC_CONTROL_IXIST 0x00000200 /* 0=FHC tells clock board it exists */
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#define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/
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#define FHC_CONTROL_LLED 0x00000040 /* 0=Left LED ON */
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#define FHC_CONTROL_MLED 0x00000020 /* 1=Middle LED ON */
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#define FHC_CONTROL_RLED 0x00000010 /* 1=Right LED */
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#define FHC_CONTROL_BPINS 0x00000003 /* Spare Bidirectional Pins */
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#define FHC_PREGS_BSR 0x30UL /* FHC Board Status Register */
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#define FHC_BSR_DA64 0x00040000 /* Port A: 0=128bit 1=64bit data path */
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#define FHC_BSR_DB64 0x00020000 /* Port B: 0=128bit 1=64bit data path */
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#define FHC_BSR_BID 0x0001e000 /* Board ID */
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#define FHC_BSR_SA 0x00001c00 /* Port A UPA Speed (from the pins) */
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#define FHC_BSR_SB 0x00000380 /* Port B UPA Speed (from the pins) */
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#define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */
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#define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */
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#define FHC_BSR_NIA 0x0000001c /* Jumper, bit 18 in PROM space */
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#define FHC_BSR_SI 0x00000001 /* Spare input pin value */
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#define FHC_PREGS_ECC 0x40UL /* FHC ECC Control Register (16 bits) */
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#define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */
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#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
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#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
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#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
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#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */
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#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */
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#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
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#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */
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#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
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#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */
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#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
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#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */
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#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
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#endif /* !(_SPARC64_FHC_H) */
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