325 lines
7.0 KiB
ArmAsm
325 lines
7.0 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AMD Memory Encryption Support
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#include <linux/linkage.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <asm/asm-offsets.h>
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#include <asm/segment.h>
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#include <asm/trapnr.h>
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.text
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.code32
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SYM_FUNC_START(get_sev_encryption_bit)
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push %ebx
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movl $0x80000000, %eax /* CPUID to check the highest leaf */
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cpuid
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cmpl $0x8000001f, %eax /* See if 0x8000001f is available */
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jb .Lno_sev
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/*
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* Check for the SEV feature:
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* CPUID Fn8000_001F[EAX] - Bit 1
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* CPUID Fn8000_001F[EBX] - Bits 5:0
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* Pagetable bit position used to indicate encryption
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*/
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movl $0x8000001f, %eax
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cpuid
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bt $1, %eax /* Check if SEV is available */
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jnc .Lno_sev
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movl $MSR_AMD64_SEV, %ecx /* Read the SEV MSR */
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rdmsr
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bt $MSR_AMD64_SEV_ENABLED_BIT, %eax /* Check if SEV is active */
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jnc .Lno_sev
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movl %ebx, %eax
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andl $0x3f, %eax /* Return the encryption bit location */
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jmp .Lsev_exit
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.Lno_sev:
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xor %eax, %eax
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.Lsev_exit:
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pop %ebx
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RET
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SYM_FUNC_END(get_sev_encryption_bit)
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/**
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* sev_es_req_cpuid - Request a CPUID value from the Hypervisor using
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* the GHCB MSR protocol
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*
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* @%eax: Register to request (0=EAX, 1=EBX, 2=ECX, 3=EDX)
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* @%edx: CPUID Function
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*
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* Returns 0 in %eax on success, non-zero on failure
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* %edx returns CPUID value on success
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*/
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SYM_CODE_START_LOCAL(sev_es_req_cpuid)
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shll $30, %eax
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orl $0x00000004, %eax
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movl $MSR_AMD64_SEV_ES_GHCB, %ecx
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wrmsr
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rep; vmmcall # VMGEXIT
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rdmsr
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/* Check response */
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movl %eax, %ecx
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andl $0x3ffff000, %ecx # Bits [12-29] MBZ
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jnz 2f
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/* Check return code */
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andl $0xfff, %eax
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cmpl $5, %eax
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jne 2f
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/* All good - return success */
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xorl %eax, %eax
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1:
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RET
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2:
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movl $-1, %eax
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jmp 1b
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SYM_CODE_END(sev_es_req_cpuid)
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SYM_CODE_START_LOCAL(startup32_vc_handler)
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pushl %eax
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pushl %ebx
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pushl %ecx
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pushl %edx
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/* Keep CPUID function in %ebx */
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movl %eax, %ebx
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/* Check if error-code == SVM_EXIT_CPUID */
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cmpl $0x72, 16(%esp)
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jne .Lfail
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movl $0, %eax # Request CPUID[fn].EAX
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movl %ebx, %edx # CPUID fn
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call sev_es_req_cpuid # Call helper
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testl %eax, %eax # Check return code
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jnz .Lfail
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movl %edx, 12(%esp) # Store result
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movl $1, %eax # Request CPUID[fn].EBX
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movl %ebx, %edx # CPUID fn
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call sev_es_req_cpuid # Call helper
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testl %eax, %eax # Check return code
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jnz .Lfail
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movl %edx, 8(%esp) # Store result
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movl $2, %eax # Request CPUID[fn].ECX
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movl %ebx, %edx # CPUID fn
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call sev_es_req_cpuid # Call helper
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testl %eax, %eax # Check return code
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jnz .Lfail
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movl %edx, 4(%esp) # Store result
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movl $3, %eax # Request CPUID[fn].EDX
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movl %ebx, %edx # CPUID fn
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call sev_es_req_cpuid # Call helper
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testl %eax, %eax # Check return code
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jnz .Lfail
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movl %edx, 0(%esp) # Store result
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/*
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* Sanity check CPUID results from the Hypervisor. See comment in
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* do_vc_no_ghcb() for more details on why this is necessary.
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*/
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/* Fail if SEV leaf not available in CPUID[0x80000000].EAX */
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cmpl $0x80000000, %ebx
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jne .Lcheck_sev
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cmpl $0x8000001f, 12(%esp)
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jb .Lfail
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jmp .Ldone
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.Lcheck_sev:
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/* Fail if SEV bit not set in CPUID[0x8000001f].EAX[1] */
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cmpl $0x8000001f, %ebx
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jne .Ldone
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btl $1, 12(%esp)
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jnc .Lfail
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.Ldone:
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popl %edx
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popl %ecx
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popl %ebx
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popl %eax
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/* Remove error code */
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addl $4, %esp
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/* Jump over CPUID instruction */
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addl $2, (%esp)
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iret
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.Lfail:
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/* Send terminate request to Hypervisor */
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movl $0x100, %eax
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xorl %edx, %edx
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movl $MSR_AMD64_SEV_ES_GHCB, %ecx
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wrmsr
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rep; vmmcall
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/* If request fails, go to hlt loop */
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hlt
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jmp .Lfail
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SYM_CODE_END(startup32_vc_handler)
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/*
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* Write an IDT entry into boot32_idt
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*
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* Parameters:
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*
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* %eax: Handler address
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* %edx: Vector number
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* %ecx: IDT address
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*/
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SYM_FUNC_START_LOCAL(startup32_set_idt_entry)
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/* IDT entry address to %ecx */
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leal (%ecx, %edx, 8), %ecx
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/* Build IDT entry, lower 4 bytes */
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movl %eax, %edx
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andl $0x0000ffff, %edx # Target code segment offset [15:0]
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orl $(__KERNEL32_CS << 16), %edx # Target code segment selector
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/* Store lower 4 bytes to IDT */
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movl %edx, (%ecx)
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/* Build IDT entry, upper 4 bytes */
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movl %eax, %edx
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andl $0xffff0000, %edx # Target code segment offset [31:16]
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orl $0x00008e00, %edx # Present, Type 32-bit Interrupt Gate
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/* Store upper 4 bytes to IDT */
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movl %edx, 4(%ecx)
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RET
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SYM_FUNC_END(startup32_set_idt_entry)
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SYM_FUNC_START(startup32_load_idt)
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push %ebp
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push %ebx
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call 1f
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1: pop %ebp
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leal (boot32_idt - 1b)(%ebp), %ebx
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/* #VC handler */
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leal (startup32_vc_handler - 1b)(%ebp), %eax
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movl $X86_TRAP_VC, %edx
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movl %ebx, %ecx
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call startup32_set_idt_entry
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/* Load IDT */
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leal (boot32_idt_desc - 1b)(%ebp), %ecx
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movl %ebx, 2(%ecx)
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lidt (%ecx)
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pop %ebx
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pop %ebp
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RET
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SYM_FUNC_END(startup32_load_idt)
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/*
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* Check for the correct C-bit position when the startup_32 boot-path is used.
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*
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* The check makes use of the fact that all memory is encrypted when paging is
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* disabled. The function creates 64 bits of random data using the RDRAND
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* instruction. RDRAND is mandatory for SEV guests, so always available. If the
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* hypervisor violates that the kernel will crash right here.
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*
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* The 64 bits of random data are stored to a memory location and at the same
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* time kept in the %eax and %ebx registers. Since encryption is always active
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* when paging is off the random data will be stored encrypted in main memory.
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*
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* Then paging is enabled. When the C-bit position is correct all memory is
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* still mapped encrypted and comparing the register values with memory will
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* succeed. An incorrect C-bit position will map all memory unencrypted, so that
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* the compare will use the encrypted random data and fail.
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*/
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SYM_FUNC_START(startup32_check_sev_cbit)
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pushl %ebx
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pushl %ebp
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call 0f
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0: popl %ebp
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/* Check for non-zero sev_status */
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movl (sev_status - 0b)(%ebp), %eax
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testl %eax, %eax
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jz 4f
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/*
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* Get two 32-bit random values - Don't bail out if RDRAND fails
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* because it is better to prevent forward progress if no random value
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* can be gathered.
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*/
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1: rdrand %eax
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jnc 1b
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2: rdrand %ebx
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jnc 2b
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/* Store to memory and keep it in the registers */
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leal (sev_check_data - 0b)(%ebp), %ebp
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movl %eax, 0(%ebp)
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movl %ebx, 4(%ebp)
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/* Enable paging to see if encryption is active */
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movl %cr0, %edx /* Backup %cr0 in %edx */
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movl $(X86_CR0_PG | X86_CR0_PE), %ecx /* Enable Paging and Protected mode */
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movl %ecx, %cr0
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cmpl %eax, 0(%ebp)
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jne 3f
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cmpl %ebx, 4(%ebp)
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jne 3f
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movl %edx, %cr0 /* Restore previous %cr0 */
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jmp 4f
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3: /* Check failed - hlt the machine */
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hlt
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jmp 3b
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4:
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popl %ebp
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popl %ebx
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RET
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SYM_FUNC_END(startup32_check_sev_cbit)
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.code64
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#include "../../kernel/sev_verify_cbit.S"
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.data
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.balign 8
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SYM_DATA(sme_me_mask, .quad 0)
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SYM_DATA(sev_status, .quad 0)
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SYM_DATA(sev_check_data, .quad 0)
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SYM_DATA_START_LOCAL(boot32_idt)
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.rept 32
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.quad 0
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.endr
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SYM_DATA_END(boot32_idt)
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SYM_DATA_START_LOCAL(boot32_idt_desc)
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.word . - boot32_idt - 1
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.long 0
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SYM_DATA_END(boot32_idt_desc)
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