99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Numascale NumaConnect-Specific Header file
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*
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* Copyright (C) 2011 Numascale AS. All rights reserved.
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*
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* Send feedback to <support@numascale.com>
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*
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*/
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#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
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#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
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#include <linux/smp.h>
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#include <linux/io.h>
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#define CSR_NODE_SHIFT 16
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#define CSR_NODE_BITS(p) (((unsigned long)(p)) << CSR_NODE_SHIFT)
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#define CSR_NODE_MASK 0x0fff /* 4K nodes */
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/* 32K CSR space, b15 indicates geo/non-geo */
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#define CSR_OFFSET_MASK 0x7fffUL
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#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
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#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
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/*
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* Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
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* when using the direct mapping on x86_64, both start and size needs to be
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* aligned with PMD_SIZE which is 2M
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*/
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#define NUMACHIP_LCSR_BASE 0x3ffffe000000ULL
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#define NUMACHIP_LCSR_LIM 0x3fffffffffffULL
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#define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
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#define NUMACHIP_LAPIC_BITS 8
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static inline void *lcsr_address(unsigned long offset)
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{
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return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
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CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
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}
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static inline unsigned int read_lcsr(unsigned long offset)
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{
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return swab32(readl(lcsr_address(offset)));
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}
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static inline void write_lcsr(unsigned long offset, unsigned int val)
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{
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writel(swab32(val), lcsr_address(offset));
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}
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/*
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* On NumaChip2, local CSR space is 16MB and starts at fixed offset below 4G
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*/
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#define NUMACHIP2_LCSR_BASE 0xf0000000UL
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#define NUMACHIP2_LCSR_SIZE 0x1000000UL
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#define NUMACHIP2_APIC_ICR 0x100000
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#define NUMACHIP2_TIMER_DEADLINE 0x200000
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#define NUMACHIP2_TIMER_INT 0x200008
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#define NUMACHIP2_TIMER_NOW 0x200018
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#define NUMACHIP2_TIMER_RESET 0x200020
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static inline void __iomem *numachip2_lcsr_address(unsigned long offset)
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{
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return (void __iomem *)__va(NUMACHIP2_LCSR_BASE |
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(offset & (NUMACHIP2_LCSR_SIZE - 1)));
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}
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static inline u32 numachip2_read32_lcsr(unsigned long offset)
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{
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return readl(numachip2_lcsr_address(offset));
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}
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static inline u64 numachip2_read64_lcsr(unsigned long offset)
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{
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return readq(numachip2_lcsr_address(offset));
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}
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static inline void numachip2_write32_lcsr(unsigned long offset, u32 val)
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{
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writel(val, numachip2_lcsr_address(offset));
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}
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static inline void numachip2_write64_lcsr(unsigned long offset, u64 val)
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{
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writeq(val, numachip2_lcsr_address(offset));
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}
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static inline unsigned int numachip2_timer(void)
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{
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return (smp_processor_id() % 48) << 6;
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}
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#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
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