345 lines
9.1 KiB
C
345 lines
9.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Interrupt descriptor table related code
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*/
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#include <linux/interrupt.h>
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#include <asm/cpu_entry_area.h>
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#include <asm/set_memory.h>
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#include <asm/traps.h>
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#include <asm/proto.h>
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#include <asm/desc.h>
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#include <asm/hw_irq.h>
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#include <asm/idtentry.h>
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#define DPL0 0x0
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#define DPL3 0x3
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#define DEFAULT_STACK 0
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#define G(_vector, _addr, _ist, _type, _dpl, _segment) \
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{ \
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.vector = _vector, \
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.bits.ist = _ist, \
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.bits.type = _type, \
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.bits.dpl = _dpl, \
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.bits.p = 1, \
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.addr = _addr, \
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.segment = _segment, \
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}
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/* Interrupt gate */
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#define INTG(_vector, _addr) \
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G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
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/* System interrupt gate */
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#define SYSG(_vector, _addr) \
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G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
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#ifdef CONFIG_X86_64
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/*
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* Interrupt gate with interrupt stack. The _ist index is the index in
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* the tss.ist[] array, but for the descriptor it needs to start at 1.
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*/
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#define ISTG(_vector, _addr, _ist) \
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G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
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#else
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#define ISTG(_vector, _addr, _ist) INTG(_vector, _addr)
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#endif
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/* Task gate */
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#define TSKG(_vector, _gdt) \
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G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
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#define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc))
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static bool idt_setup_done __initdata;
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/*
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* Early traps running on the DEFAULT_STACK because the other interrupt
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* stacks work only after cpu_init().
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*/
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static const __initconst struct idt_data early_idts[] = {
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INTG(X86_TRAP_DB, asm_exc_debug),
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SYSG(X86_TRAP_BP, asm_exc_int3),
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#ifdef CONFIG_X86_32
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/*
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* Not possible on 64-bit. See idt_setup_early_pf() for details.
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*/
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INTG(X86_TRAP_PF, asm_exc_page_fault),
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#endif
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#ifdef CONFIG_INTEL_TDX_GUEST
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INTG(X86_TRAP_VE, asm_exc_virtualization_exception),
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#endif
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};
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/*
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* The default IDT entries which are set up in trap_init() before
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* cpu_init() is invoked. Interrupt stacks cannot be used at that point and
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* the traps which use them are reinitialized with IST after cpu_init() has
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* set up TSS.
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*/
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static const __initconst struct idt_data def_idts[] = {
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INTG(X86_TRAP_DE, asm_exc_divide_error),
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ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI),
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INTG(X86_TRAP_BR, asm_exc_bounds),
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INTG(X86_TRAP_UD, asm_exc_invalid_op),
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INTG(X86_TRAP_NM, asm_exc_device_not_available),
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INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun),
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INTG(X86_TRAP_TS, asm_exc_invalid_tss),
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INTG(X86_TRAP_NP, asm_exc_segment_not_present),
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INTG(X86_TRAP_SS, asm_exc_stack_segment),
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INTG(X86_TRAP_GP, asm_exc_general_protection),
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INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug),
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INTG(X86_TRAP_MF, asm_exc_coprocessor_error),
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INTG(X86_TRAP_AC, asm_exc_alignment_check),
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INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error),
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#ifdef CONFIG_X86_32
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TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS),
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#else
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ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF),
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#endif
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ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB),
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#ifdef CONFIG_X86_MCE
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ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE),
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#endif
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#ifdef CONFIG_X86_KERNEL_IBT
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INTG(X86_TRAP_CP, asm_exc_control_protection),
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#endif
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC),
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#endif
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SYSG(X86_TRAP_OF, asm_exc_overflow),
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#if defined(CONFIG_IA32_EMULATION)
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SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat),
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#elif defined(CONFIG_X86_32)
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SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32),
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#endif
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};
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/*
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* The APIC and SMP idt entries
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*/
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static const __initconst struct idt_data apic_idts[] = {
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#ifdef CONFIG_SMP
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INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi),
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INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function),
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INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single),
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INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup),
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INTG(REBOOT_VECTOR, asm_sysvec_reboot),
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#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal),
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold),
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error),
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt),
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INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi),
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# ifdef CONFIG_HAVE_KVM
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INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi),
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INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi),
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INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi),
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# endif
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# ifdef CONFIG_IRQ_WORK
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INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work),
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# endif
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INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt),
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INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt),
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#endif
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};
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/* Must be page-aligned because the real IDT is used in the cpu entry area */
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static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
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static struct desc_ptr idt_descr __ro_after_init = {
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.size = IDT_TABLE_SIZE - 1,
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.address = (unsigned long) idt_table,
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};
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void load_current_idt(void)
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{
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lockdep_assert_irqs_disabled();
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load_idt(&idt_descr);
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}
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#ifdef CONFIG_X86_F00F_BUG
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bool idt_is_f00f_address(unsigned long address)
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{
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return ((address - idt_descr.address) >> 3) == 6;
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}
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#endif
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static __init void
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idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
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{
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gate_desc desc;
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for (; size > 0; t++, size--) {
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idt_init_desc(&desc, t);
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write_idt_entry(idt, t->vector, &desc);
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if (sys)
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set_bit(t->vector, system_vectors);
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}
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}
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static __init void set_intr_gate(unsigned int n, const void *addr)
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{
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struct idt_data data;
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init_idt_data(&data, n, addr);
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idt_setup_from_table(idt_table, &data, 1, false);
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}
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/**
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* idt_setup_early_traps - Initialize the idt table with early traps
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*
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* On X8664 these traps do not use interrupt stacks as they can't work
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* before cpu_init() is invoked and sets up TSS. The IST variants are
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* installed after that.
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*/
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void __init idt_setup_early_traps(void)
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{
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idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
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true);
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load_idt(&idt_descr);
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}
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/**
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* idt_setup_traps - Initialize the idt table with default traps
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*/
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void __init idt_setup_traps(void)
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{
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idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
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}
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#ifdef CONFIG_X86_64
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/*
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* Early traps running on the DEFAULT_STACK because the other interrupt
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* stacks work only after cpu_init().
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*/
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static const __initconst struct idt_data early_pf_idts[] = {
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INTG(X86_TRAP_PF, asm_exc_page_fault),
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};
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/**
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* idt_setup_early_pf - Initialize the idt table with early pagefault handler
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*
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* On X8664 this does not use interrupt stacks as they can't work before
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* cpu_init() is invoked and sets up TSS. The IST variant is installed
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* after that.
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*
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* Note, that X86_64 cannot install the real #PF handler in
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* idt_setup_early_traps() because the memory initialization needs the #PF
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* handler from the early_idt_handler_array to initialize the early page
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* tables.
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*/
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void __init idt_setup_early_pf(void)
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{
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idt_setup_from_table(idt_table, early_pf_idts,
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ARRAY_SIZE(early_pf_idts), true);
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}
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#endif
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static void __init idt_map_in_cea(void)
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{
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/*
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* Set the IDT descriptor to a fixed read-only location in the cpu
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* entry area, so that the "sidt" instruction will not leak the
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* location of the kernel, and to defend the IDT against arbitrary
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* memory write vulnerabilities.
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*/
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cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
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PAGE_KERNEL_RO);
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idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
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}
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/**
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* idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
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*/
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void __init idt_setup_apic_and_irq_gates(void)
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{
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int i = FIRST_EXTERNAL_VECTOR;
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void *entry;
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idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
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for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
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entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR);
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set_intr_gate(i, entry);
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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for_each_clear_bit_from(i, system_vectors, NR_VECTORS) {
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/*
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* Don't set the non assigned system vectors in the
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* system_vectors bitmap. Otherwise they show up in
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* /proc/interrupts.
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*/
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entry = spurious_entries_start + IDT_ALIGN * (i - FIRST_SYSTEM_VECTOR);
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set_intr_gate(i, entry);
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}
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#endif
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/* Map IDT into CPU entry area and reload it. */
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idt_map_in_cea();
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load_idt(&idt_descr);
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/* Make the IDT table read only */
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set_memory_ro((unsigned long)&idt_table, 1);
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idt_setup_done = true;
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}
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/**
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* idt_setup_early_handler - Initializes the idt table with early handlers
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*/
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void __init idt_setup_early_handler(void)
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{
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int i;
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for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
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set_intr_gate(i, early_idt_handler_array[i]);
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#ifdef CONFIG_X86_32
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for ( ; i < NR_VECTORS; i++)
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set_intr_gate(i, early_ignore_irq);
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#endif
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load_idt(&idt_descr);
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}
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/**
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* idt_invalidate - Invalidate interrupt descriptor table
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*/
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void idt_invalidate(void)
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{
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static const struct desc_ptr idt = { .address = 0, .size = 0 };
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load_idt(&idt);
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}
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void __init alloc_intr_gate(unsigned int n, const void *addr)
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{
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if (WARN_ON(n < FIRST_SYSTEM_VECTOR))
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return;
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if (WARN_ON(idt_setup_done))
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return;
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if (!WARN_ON(test_and_set_bit(n, system_vectors)))
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set_intr_gate(n, addr);
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}
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