264 lines
7.1 KiB
C
264 lines
7.1 KiB
C
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/*
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* include/asm-xtensa/atomic.h
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*
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* Atomic operations that C can't guarantee us. Useful for resource counting..
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2008 Tensilica Inc.
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*/
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#ifndef _XTENSA_ATOMIC_H
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#define _XTENSA_ATOMIC_H
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#include <linux/stringify.h>
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#include <linux/types.h>
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#include <asm/processor.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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/*
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* This Xtensa implementation assumes that the right mechanism
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* for exclusion is for locking interrupts to level EXCM_LEVEL.
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*
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* Locking interrupts looks like this:
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*
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* rsil a14, TOPLEVEL
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* <code>
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* wsr a14, PS
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* rsync
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*
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* Note that a14 is used here because the register allocation
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* done by the compiler is not guaranteed and a window overflow
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* may not occur between the rsil and wsr instructions. By using
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* a14 in the rsil, the machine is guaranteed to be in a state
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* where no register reference will cause an overflow.
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*/
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/**
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* atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v.
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*/
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#define arch_atomic_read(v) READ_ONCE((v)->counter)
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/**
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* atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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#define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
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#if XCHAL_HAVE_EXCLUSIVE
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#define ATOMIC_OP(op) \
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static inline void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32ex %[tmp], %[addr]\n" \
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" " #op " %[result], %[tmp], %[i]\n" \
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" s32ex %[result], %[addr]\n" \
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" getex %[result]\n" \
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" beqz %[result], 1b\n" \
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: [result] "=&a" (result), [tmp] "=&a" (tmp) \
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: [i] "a" (i), [addr] "a" (v) \
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: "memory" \
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); \
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} \
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#define ATOMIC_OP_RETURN(op) \
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static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32ex %[tmp], %[addr]\n" \
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" " #op " %[result], %[tmp], %[i]\n" \
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" s32ex %[result], %[addr]\n" \
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" getex %[result]\n" \
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" beqz %[result], 1b\n" \
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" " #op " %[result], %[tmp], %[i]\n" \
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: [result] "=&a" (result), [tmp] "=&a" (tmp) \
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: [i] "a" (i), [addr] "a" (v) \
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: "memory" \
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); \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(op) \
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static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32ex %[tmp], %[addr]\n" \
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" " #op " %[result], %[tmp], %[i]\n" \
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" s32ex %[result], %[addr]\n" \
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" getex %[result]\n" \
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" beqz %[result], 1b\n" \
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: [result] "=&a" (result), [tmp] "=&a" (tmp) \
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: [i] "a" (i), [addr] "a" (v) \
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: "memory" \
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); \
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\
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return tmp; \
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}
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#elif XCHAL_HAVE_S32C1I
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#define ATOMIC_OP(op) \
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static inline void arch_atomic_##op(int i, atomic_t * v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32i %[tmp], %[mem]\n" \
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" wsr %[tmp], scompare1\n" \
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" " #op " %[result], %[tmp], %[i]\n" \
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" s32c1i %[result], %[mem]\n" \
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" bne %[result], %[tmp], 1b\n" \
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: [result] "=&a" (result), [tmp] "=&a" (tmp), \
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[mem] "+m" (*v) \
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: [i] "a" (i) \
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: "memory" \
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); \
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} \
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#define ATOMIC_OP_RETURN(op) \
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static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32i %[tmp], %[mem]\n" \
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" wsr %[tmp], scompare1\n" \
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" " #op " %[result], %[tmp], %[i]\n" \
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" s32c1i %[result], %[mem]\n" \
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" bne %[result], %[tmp], 1b\n" \
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" " #op " %[result], %[result], %[i]\n" \
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: [result] "=&a" (result), [tmp] "=&a" (tmp), \
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[mem] "+m" (*v) \
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: [i] "a" (i) \
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: "memory" \
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); \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(op) \
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static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32i %[tmp], %[mem]\n" \
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" wsr %[tmp], scompare1\n" \
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" " #op " %[result], %[tmp], %[i]\n" \
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" s32c1i %[result], %[mem]\n" \
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" bne %[result], %[tmp], 1b\n" \
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: [result] "=&a" (result), [tmp] "=&a" (tmp), \
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[mem] "+m" (*v) \
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: [i] "a" (i) \
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: "memory" \
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); \
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\
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return result; \
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}
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#else /* XCHAL_HAVE_S32C1I */
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#define ATOMIC_OP(op) \
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static inline void arch_atomic_##op(int i, atomic_t * v) \
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{ \
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unsigned int vval; \
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\
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__asm__ __volatile__( \
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" rsil a14, "__stringify(TOPLEVEL)"\n" \
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" l32i %[result], %[mem]\n" \
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" " #op " %[result], %[result], %[i]\n" \
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" s32i %[result], %[mem]\n" \
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" wsr a14, ps\n" \
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" rsync\n" \
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: [result] "=&a" (vval), [mem] "+m" (*v) \
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: [i] "a" (i) \
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: "a14", "memory" \
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); \
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} \
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#define ATOMIC_OP_RETURN(op) \
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static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
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{ \
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unsigned int vval; \
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\
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__asm__ __volatile__( \
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" rsil a14,"__stringify(TOPLEVEL)"\n" \
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" l32i %[result], %[mem]\n" \
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" " #op " %[result], %[result], %[i]\n" \
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" s32i %[result], %[mem]\n" \
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" wsr a14, ps\n" \
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" rsync\n" \
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: [result] "=&a" (vval), [mem] "+m" (*v) \
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: [i] "a" (i) \
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: "a14", "memory" \
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); \
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\
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return vval; \
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}
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#define ATOMIC_FETCH_OP(op) \
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static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
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{ \
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unsigned int tmp, vval; \
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\
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__asm__ __volatile__( \
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" rsil a14,"__stringify(TOPLEVEL)"\n" \
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" l32i %[result], %[mem]\n" \
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" " #op " %[tmp], %[result], %[i]\n" \
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" s32i %[tmp], %[mem]\n" \
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" wsr a14, ps\n" \
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" rsync\n" \
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: [result] "=&a" (vval), [tmp] "=&a" (tmp), \
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[mem] "+m" (*v) \
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: [i] "a" (i) \
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: "a14", "memory" \
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); \
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\
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return vval; \
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}
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#endif /* XCHAL_HAVE_S32C1I */
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OP_RETURN(op)
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ATOMIC_OPS(add)
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ATOMIC_OPS(sub)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(and)
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ATOMIC_OPS(or)
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ATOMIC_OPS(xor)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#define arch_atomic_cmpxchg(v, o, n) ((int)arch_cmpxchg(&((v)->counter), (o), (n)))
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#define arch_atomic_xchg(v, new) (arch_xchg(&((v)->counter), new))
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#endif /* _XTENSA_ATOMIC_H */
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