400 lines
11 KiB
C
400 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020-2022 HabanaLabs, Ltd.
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* All Rights Reserved.
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*/
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#include "../habanalabs.h"
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#include "../../include/hw_ip/mmu/mmu_general.h"
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#include <linux/slab.h>
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static struct pgt_info *hl_mmu_v2_hr_get_pgt_info(struct hl_ctx *ctx, u64 phys_hop_addr)
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{
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struct pgt_info *pgt_info = NULL;
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hash_for_each_possible(ctx->hr_mmu_phys_hash, pgt_info, node,
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(unsigned long) phys_hop_addr)
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if (phys_hop_addr == pgt_info->phys_addr)
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break;
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return pgt_info;
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}
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static void hl_mmu_v2_hr_add_pgt_info(struct hl_ctx *ctx, struct pgt_info *pgt_info,
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dma_addr_t phys_addr)
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{
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hash_add(ctx->hr_mmu_phys_hash, &pgt_info->node, phys_addr);
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}
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static struct pgt_info *hl_mmu_v2_hr_get_hop0_pgt_info(struct hl_ctx *ctx)
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{
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return &ctx->hdev->mmu_priv.hr.mmu_asid_hop0[ctx->asid];
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}
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/**
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* hl_mmu_v2_hr_init() - initialize the MMU module.
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* @hdev: habanalabs device structure.
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*
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* This function does the following:
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* - Create a pool of pages for pgt_infos.
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* - Create a shadow table for pgt
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*
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* Return: 0 for success, non-zero for failure.
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*/
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static inline int hl_mmu_v2_hr_init(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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return hl_mmu_hr_init(hdev, &hdev->mmu_priv.hr, prop->mmu_hop_table_size,
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prop->mmu_pgt_size);
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}
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/**
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* hl_mmu_v2_hr_fini() - release the MMU module.
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* @hdev: habanalabs device structure.
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*
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* This function does the following:
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* - Disable MMU in H/W.
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* - Free the pgt_infos pool.
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*
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* All contexts should be freed before calling this function.
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*/
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static inline void hl_mmu_v2_hr_fini(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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hl_mmu_hr_fini(hdev, &hdev->mmu_priv.hr, prop->mmu_hop_table_size);
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}
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/**
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* hl_mmu_v2_hr_ctx_init() - initialize a context for using the MMU module.
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* @ctx: pointer to the context structure to initialize.
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*
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* Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
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* page tables hops related to this context.
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* Return: 0 on success, non-zero otherwise.
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*/
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static int hl_mmu_v2_hr_ctx_init(struct hl_ctx *ctx)
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{
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hash_init(ctx->hr_mmu_phys_hash);
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return 0;
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}
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/*
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* hl_mmu_v2_hr_ctx_fini - disable a ctx from using the mmu module
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*
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* @ctx: pointer to the context structure
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*
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* This function does the following:
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* - Free any pgts which were not freed yet
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* - Free the mutex
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* - Free DRAM default page mapping hops
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*/
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static void hl_mmu_v2_hr_ctx_fini(struct hl_ctx *ctx)
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{
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struct hl_device *hdev = ctx->hdev;
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struct pgt_info *pgt_info;
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struct hlist_node *tmp;
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int i;
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if (!hash_empty(ctx->hr_mmu_phys_hash))
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dev_err(hdev->dev, "ctx %d is freed while it has pgts in use\n",
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ctx->asid);
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hash_for_each_safe(ctx->hr_mmu_phys_hash, i, tmp, pgt_info, node) {
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dev_err_ratelimited(hdev->dev,
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"pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n",
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pgt_info->phys_addr, ctx->asid, pgt_info->num_of_ptes);
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hl_mmu_hr_free_hop_remove_pgt(pgt_info, &ctx->hdev->mmu_priv.hr,
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ctx->hdev->asic_prop.mmu_hop_table_size);
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}
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}
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static int _hl_mmu_v2_hr_unmap(struct hl_ctx *ctx,
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u64 virt_addr, bool is_dram_addr)
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{
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u64 curr_pte, scrambled_virt_addr, hop_pte_phys_addr[MMU_ARCH_6_HOPS] = { 0 };
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struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL };
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struct hl_device *hdev = ctx->hdev;
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struct asic_fixed_properties *prop;
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struct hl_mmu_properties *mmu_prop;
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bool is_huge = false;
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int i, hop_last;
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prop = &hdev->asic_prop;
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/* shifts and masks are the same in PMMU and HMMU, use one of them */
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mmu_prop = is_dram_addr ? &prop->dmmu : &prop->pmmu;
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hop_last = mmu_prop->num_hops - 1;
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scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
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curr_pte = 0;
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for (i = 0 ; i < mmu_prop->num_hops ; i++) {
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/* we get HOP0 differently, it doesn't need curr_pte */
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if (i == 0)
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hops_pgt_info[i] = hl_mmu_v2_hr_get_hop0_pgt_info(ctx);
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else
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hops_pgt_info[i] = hl_mmu_hr_get_next_hop_pgt_info(ctx,
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&ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs, curr_pte);
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if (!hops_pgt_info[i])
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goto not_mapped;
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hop_pte_phys_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
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hops_pgt_info[i]->phys_addr,
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scrambled_virt_addr);
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if (hop_pte_phys_addr[i] == U64_MAX)
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return -EFAULT;
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curr_pte = *(u64 *) (uintptr_t) hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
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hop_pte_phys_addr[i],
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ctx->hdev->asic_prop.mmu_hop_table_size);
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if ((i < hop_last) && (curr_pte & mmu_prop->last_mask)) {
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hop_last = i;
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is_huge = true;
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break;
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}
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}
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if (is_dram_addr && !is_huge) {
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dev_err(hdev->dev, "DRAM unmapping should use huge pages only\n");
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return -EFAULT;
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}
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if (!(curr_pte & PAGE_PRESENT_MASK))
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goto not_mapped;
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for (i = hop_last ; i > 0 ; i--) {
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hl_mmu_hr_clear_pte(ctx, hops_pgt_info[i], hop_pte_phys_addr[i],
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ctx->hdev->asic_prop.mmu_hop_table_size);
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if (hl_mmu_hr_put_pte(ctx, hops_pgt_info[i], &ctx->hdev->mmu_priv.hr,
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ctx->hdev->asic_prop.mmu_hop_table_size))
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goto mapped;
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}
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hl_mmu_hr_clear_pte(ctx, hops_pgt_info[0], hop_pte_phys_addr[0],
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ctx->hdev->asic_prop.mmu_hop_table_size);
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mapped:
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return 0;
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not_mapped:
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dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n", virt_addr);
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return -EINVAL;
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}
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static int hl_mmu_v2_get_last_hop(struct hl_mmu_properties *mmu_prop, u32 page_size)
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{
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int hop;
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for (hop = (mmu_prop->num_hops - 1); hop; hop--) {
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if (mmu_prop->hop_shifts[hop] == 0)
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continue;
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if (page_size <= (1 << mmu_prop->hop_shifts[hop]))
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break;
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}
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return hop;
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}
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static int _hl_mmu_v2_hr_map(struct hl_ctx *ctx,
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u64 virt_addr, u64 phys_addr,
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u32 page_size, bool is_dram_addr)
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{
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u64 hop_pte_phys_addr[MMU_ARCH_6_HOPS] = { 0 },
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curr_pte = 0, scrambled_virt_addr, scrambled_phys_addr;
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struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL };
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bool hop_new[MMU_ARCH_6_HOPS] = { false };
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struct hl_device *hdev = ctx->hdev;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct hl_mmu_properties *mmu_prop;
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int i, hop_last, rc = -ENOMEM;
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/*
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* This mapping function can map a page or a huge page. For huge page
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* there are only 4 hops rather than 5. Currently the DRAM allocation
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* uses huge pages only but user memory could have been allocated with
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* one of the two page sizes. Since this is a common code for all the
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* three cases, we need this hugs page check.
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*/
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if (is_dram_addr)
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mmu_prop = &prop->dmmu;
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else if (page_size == prop->pmmu_huge.page_size)
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mmu_prop = &prop->pmmu_huge;
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else
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mmu_prop = &prop->pmmu;
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hop_last = hl_mmu_v2_get_last_hop(mmu_prop, page_size);
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if (hop_last <= 0) {
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dev_err(ctx->hdev->dev, "Invalid last HOP %d\n", hop_last);
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return -EFAULT;
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}
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scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
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scrambled_phys_addr = hdev->asic_funcs->scramble_addr(hdev, phys_addr);
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for (i = 0 ; i <= hop_last ; i++) {
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if (i == 0)
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hops_pgt_info[i] = hl_mmu_v2_hr_get_hop0_pgt_info(ctx);
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else
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hops_pgt_info[i] = hl_mmu_hr_get_alloc_next_hop(ctx,
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&ctx->hdev->mmu_priv.hr,
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&ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs,
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mmu_prop, curr_pte, &hop_new[i]);
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if (!hops_pgt_info[i])
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goto err;
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hop_pte_phys_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
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hops_pgt_info[i]->phys_addr,
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scrambled_virt_addr);
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curr_pte = *(u64 *) (uintptr_t) hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
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hop_pte_phys_addr[i],
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ctx->hdev->asic_prop.mmu_hop_table_size);
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}
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if (curr_pte & PAGE_PRESENT_MASK) {
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dev_err(hdev->dev, "mapping already exists for virt_addr 0x%llx\n",
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scrambled_virt_addr);
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for (i = 0 ; i <= hop_last ; i++)
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dev_dbg(hdev->dev, "hop%d pte: 0x%llx (0x%llx)\n",
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i,
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*(u64 *) (uintptr_t)
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hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
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hop_pte_phys_addr[i],
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ctx->hdev->asic_prop.mmu_hop_table_size),
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hop_pte_phys_addr[i]);
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rc = -EINVAL;
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goto err;
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}
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curr_pte = (scrambled_phys_addr & HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask
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| PAGE_PRESENT_MASK;
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/* Write the PTEs */
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hl_mmu_hr_write_pte(ctx, hops_pgt_info[hop_last], hop_pte_phys_addr[hop_last], curr_pte,
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ctx->hdev->asic_prop.mmu_hop_table_size);
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/* for each new hop, add its address to the table of previous-hop */
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for (i = 1 ; i <= hop_last ; i++) {
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if (hop_new[i]) {
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curr_pte = (hops_pgt_info[i]->phys_addr & HOP_PHYS_ADDR_MASK) |
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PAGE_PRESENT_MASK;
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hl_mmu_hr_write_pte(ctx, hops_pgt_info[i - 1], hop_pte_phys_addr[i - 1],
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curr_pte, ctx->hdev->asic_prop.mmu_hop_table_size);
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if (i - 1)
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hl_mmu_hr_get_pte(ctx, &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs,
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hops_pgt_info[i - 1]->phys_addr);
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}
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}
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hl_mmu_hr_get_pte(ctx, &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs,
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hops_pgt_info[hop_last]->phys_addr);
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return 0;
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err:
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for (i = 1 ; i <= hop_last ; i++)
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if (hop_new[i] && hops_pgt_info[i])
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hl_mmu_hr_free_hop_remove_pgt(hops_pgt_info[i], &ctx->hdev->mmu_priv.hr,
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ctx->hdev->asic_prop.mmu_hop_table_size);
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return rc;
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}
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/*
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* hl_mmu_v2_swap_out - marks all mapping of the given ctx as swapped out
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*
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* @ctx: pointer to the context structure
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*
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*/
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static void hl_mmu_v2_hr_swap_out(struct hl_ctx *ctx)
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{
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}
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/*
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* hl_mmu_v2_swap_in - marks all mapping of the given ctx as swapped in
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*
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* @ctx: pointer to the context structure
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*
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*/
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static void hl_mmu_v2_hr_swap_in(struct hl_ctx *ctx)
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{
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}
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static int hl_mmu_v2_hr_get_tlb_mapping_params(struct hl_device *hdev,
|
||
|
|
struct hl_mmu_properties **mmu_prop,
|
||
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|
struct hl_mmu_hop_info *hops,
|
||
|
|
u64 virt_addr, bool *is_huge)
|
||
|
|
{
|
||
|
|
struct asic_fixed_properties *prop = &hdev->asic_prop;
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||
|
|
bool is_dram_addr, is_pmmu_addr, is_pmmu_h_addr;
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||
|
|
|
||
|
|
is_dram_addr = hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
|
||
|
|
prop->dmmu.start_addr,
|
||
|
|
prop->dmmu.end_addr);
|
||
|
|
is_pmmu_addr = hl_mem_area_inside_range(virt_addr, prop->pmmu.page_size,
|
||
|
|
prop->pmmu.start_addr,
|
||
|
|
prop->pmmu.end_addr);
|
||
|
|
is_pmmu_h_addr = hl_mem_area_inside_range(virt_addr,
|
||
|
|
prop->pmmu_huge.page_size,
|
||
|
|
prop->pmmu_huge.start_addr,
|
||
|
|
prop->pmmu_huge.end_addr);
|
||
|
|
if (is_dram_addr) {
|
||
|
|
*mmu_prop = &prop->dmmu;
|
||
|
|
*is_huge = true;
|
||
|
|
hops->range_type = HL_VA_RANGE_TYPE_DRAM;
|
||
|
|
} else if (is_pmmu_addr) {
|
||
|
|
*mmu_prop = &prop->pmmu;
|
||
|
|
*is_huge = false;
|
||
|
|
hops->range_type = HL_VA_RANGE_TYPE_HOST;
|
||
|
|
} else if (is_pmmu_h_addr) {
|
||
|
|
*mmu_prop = &prop->pmmu_huge;
|
||
|
|
*is_huge = true;
|
||
|
|
hops->range_type = HL_VA_RANGE_TYPE_HOST_HUGE;
|
||
|
|
} else {
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hl_mmu_v2_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
|
||
|
|
struct hl_mmu_hop_info *hops)
|
||
|
|
{
|
||
|
|
return hl_mmu_hr_get_tlb_info(ctx, virt_addr, hops,
|
||
|
|
&ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* hl_mmu_v2_prepare - prepare mmu_if for working with mmu v2
|
||
|
|
*
|
||
|
|
* @hdev: pointer to the device structure
|
||
|
|
* @mmu_if: pointer to the mmu interface structure
|
||
|
|
*/
|
||
|
|
void hl_mmu_v2_hr_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu)
|
||
|
|
{
|
||
|
|
mmu->init = hl_mmu_v2_hr_init;
|
||
|
|
mmu->fini = hl_mmu_v2_hr_fini;
|
||
|
|
mmu->ctx_init = hl_mmu_v2_hr_ctx_init;
|
||
|
|
mmu->ctx_fini = hl_mmu_v2_hr_ctx_fini;
|
||
|
|
mmu->map = _hl_mmu_v2_hr_map;
|
||
|
|
mmu->unmap = _hl_mmu_v2_hr_unmap;
|
||
|
|
mmu->flush = hl_mmu_hr_flush;
|
||
|
|
mmu->swap_out = hl_mmu_v2_hr_swap_out;
|
||
|
|
mmu->swap_in = hl_mmu_v2_hr_swap_in;
|
||
|
|
mmu->get_tlb_info = hl_mmu_v2_hr_get_tlb_info;
|
||
|
|
mmu->hr_funcs.get_hop0_pgt_info = hl_mmu_v2_hr_get_hop0_pgt_info;
|
||
|
|
mmu->hr_funcs.get_pgt_info = hl_mmu_v2_hr_get_pgt_info;
|
||
|
|
mmu->hr_funcs.add_pgt_info = hl_mmu_v2_hr_add_pgt_info;
|
||
|
|
mmu->hr_funcs.get_tlb_mapping_params = hl_mmu_v2_hr_get_tlb_mapping_params;
|
||
|
|
}
|