62 lines
2.9 KiB
C
62 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2020 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef GAUDI2_REG_MAP_H_
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#define GAUDI2_REG_MAP_H_
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/*
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* PSOC scratch-pad registers
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*/
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#define mmHW_STATE mmCPU_IF_KMD_HW_DIRTY_STATUS
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#define mmPID_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
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#define mmARM_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
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#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
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#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
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#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
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#define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
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#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
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#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
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#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_9
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#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
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#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11
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#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12
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#define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14
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/*
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* Single scratchpad register used for all ARCs to notify dccm queue full event to FW.
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* So a new event would overwrite any unhandled previous event. In other words, incase
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* of multiple events before previous ones are handled, last one would be considered.
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*/
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#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
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#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
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#define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19
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#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
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#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
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#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23
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#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24
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#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
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#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
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#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
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#define mmPPBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
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#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
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#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
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#define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0
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#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
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#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
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#define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0
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#define mmPID_CMD_REQ_REG_HI mmPSOC_PID_PID_CMD_1
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#define mmPID_CMD_RSP_REG mmPSOC_PID_PID_CMD_2
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#define mmPID_CMD_RSP_REG_HI mmPSOC_PID_PID_CMD_3
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#define mmPID_CMD_TELEMETRY_REG_0 mmPSOC_PID_PID_CMD_4
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#define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5
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#define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6
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#define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7
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#define mmWD_GPIO_OUTSET_REG mmPSOC_GPIO3_OUTENSET
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#define mmWD_GPIO_DATAOUT_REG mmPSOC_GPIO3_DATAOUT
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#define mmSTM_PROFILER_SPE_REG mmPSOC_STM_STMSPER
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#endif /* GAUDI2_REG_MAP_H_ */
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