494 lines
13 KiB
C
494 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DWC AHCI SATA Platform driver
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*
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* Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
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*/
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#include <linux/ahci_platform.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/libata.h>
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#include <linux/log2.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include "ahci.h"
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#define DRV_NAME "ahci-dwc"
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#define AHCI_DWC_FBS_PMPN_MAX 15
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/* DWC AHCI SATA controller specific registers */
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#define AHCI_DWC_HOST_OOBR 0xbc
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#define AHCI_DWC_HOST_OOB_WE BIT(31)
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#define AHCI_DWC_HOST_CWMIN_MASK GENMASK(30, 24)
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#define AHCI_DWC_HOST_CWMAX_MASK GENMASK(23, 16)
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#define AHCI_DWC_HOST_CIMIN_MASK GENMASK(15, 8)
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#define AHCI_DWC_HOST_CIMAX_MASK GENMASK(7, 0)
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#define AHCI_DWC_HOST_GPCR 0xd0
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#define AHCI_DWC_HOST_GPSR 0xd4
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#define AHCI_DWC_HOST_TIMER1MS 0xe0
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#define AHCI_DWC_HOST_TIMV_MASK GENMASK(19, 0)
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#define AHCI_DWC_HOST_GPARAM1R 0xe8
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#define AHCI_DWC_HOST_ALIGN_M BIT(31)
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#define AHCI_DWC_HOST_RX_BUFFER BIT(30)
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#define AHCI_DWC_HOST_PHY_DATA_MASK GENMASK(29, 28)
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#define AHCI_DWC_HOST_PHY_RST BIT(27)
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#define AHCI_DWC_HOST_PHY_CTRL_MASK GENMASK(26, 21)
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#define AHCI_DWC_HOST_PHY_STAT_MASK GENMASK(20, 15)
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#define AHCI_DWC_HOST_LATCH_M BIT(14)
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#define AHCI_DWC_HOST_PHY_TYPE_MASK GENMASK(13, 11)
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#define AHCI_DWC_HOST_RET_ERR BIT(10)
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#define AHCI_DWC_HOST_AHB_ENDIAN_MASK GENMASK(9, 8)
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#define AHCI_DWC_HOST_S_HADDR BIT(7)
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#define AHCI_DWC_HOST_M_HADDR BIT(6)
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#define AHCI_DWC_HOST_S_HDATA_MASK GENMASK(5, 3)
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#define AHCI_DWC_HOST_M_HDATA_MASK GENMASK(2, 0)
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#define AHCI_DWC_HOST_GPARAM2R 0xec
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#define AHCI_DWC_HOST_FBS_MEM_S BIT(19)
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#define AHCI_DWC_HOST_FBS_PMPN_MASK GENMASK(17, 16)
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#define AHCI_DWC_HOST_FBS_SUP BIT(15)
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#define AHCI_DWC_HOST_DEV_CP BIT(14)
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#define AHCI_DWC_HOST_DEV_MP BIT(13)
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#define AHCI_DWC_HOST_ENCODE_M BIT(12)
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#define AHCI_DWC_HOST_RXOOB_CLK_M BIT(11)
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#define AHCI_DWC_HOST_RXOOB_M BIT(10)
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#define AHCI_DWC_HOST_TXOOB_M BIT(9)
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#define AHCI_DWC_HOST_RXOOB_M BIT(10)
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#define AHCI_DWC_HOST_RXOOB_CLK_MASK GENMASK(8, 0)
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#define AHCI_DWC_HOST_PPARAMR 0xf0
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#define AHCI_DWC_HOST_TX_MEM_M BIT(11)
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#define AHCI_DWC_HOST_TX_MEM_S BIT(10)
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#define AHCI_DWC_HOST_RX_MEM_M BIT(9)
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#define AHCI_DWC_HOST_RX_MEM_S BIT(8)
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#define AHCI_DWC_HOST_TXFIFO_DEPTH GENMASK(7, 4)
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#define AHCI_DWC_HOST_RXFIFO_DEPTH GENMASK(3, 0)
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#define AHCI_DWC_HOST_TESTR 0xf4
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#define AHCI_DWC_HOST_PSEL_MASK GENMASK(18, 16)
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#define AHCI_DWC_HOST_TEST_IF BIT(0)
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#define AHCI_DWC_HOST_VERSIONR 0xf8
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#define AHCI_DWC_HOST_IDR 0xfc
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#define AHCI_DWC_PORT_DMACR 0x70
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#define AHCI_DWC_PORT_RXABL_MASK GENMASK(15, 12)
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#define AHCI_DWC_PORT_TXABL_MASK GENMASK(11, 8)
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#define AHCI_DWC_PORT_RXTS_MASK GENMASK(7, 4)
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#define AHCI_DWC_PORT_TXTS_MASK GENMASK(3, 0)
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#define AHCI_DWC_PORT_PHYCR 0x74
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#define AHCI_DWC_PORT_PHYSR 0x78
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/* Baikal-T1 AHCI SATA specific registers */
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#define AHCI_BT1_HOST_PHYCR AHCI_DWC_HOST_GPCR
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#define AHCI_BT1_HOST_MPLM_MASK GENMASK(29, 23)
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#define AHCI_BT1_HOST_LOSDT_MASK GENMASK(22, 20)
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#define AHCI_BT1_HOST_CRR BIT(19)
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#define AHCI_BT1_HOST_CRW BIT(18)
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#define AHCI_BT1_HOST_CRCD BIT(17)
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#define AHCI_BT1_HOST_CRCA BIT(16)
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#define AHCI_BT1_HOST_CRDI_MASK GENMASK(15, 0)
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#define AHCI_BT1_HOST_PHYSR AHCI_DWC_HOST_GPSR
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#define AHCI_BT1_HOST_CRA BIT(16)
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#define AHCI_BT1_HOST_CRDO_MASK GENMASK(15, 0)
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struct ahci_dwc_plat_data {
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unsigned int pflags;
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unsigned int hflags;
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int (*init)(struct ahci_host_priv *hpriv);
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int (*reinit)(struct ahci_host_priv *hpriv);
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void (*clear)(struct ahci_host_priv *hpriv);
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};
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struct ahci_dwc_host_priv {
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const struct ahci_dwc_plat_data *pdata;
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struct platform_device *pdev;
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u32 timv;
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u32 dmacr[AHCI_MAX_PORTS];
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};
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static int ahci_bt1_init(struct ahci_host_priv *hpriv)
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{
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struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
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int ret;
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/* APB, application and reference clocks are required */
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if (!ahci_platform_find_clk(hpriv, "pclk") ||
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!ahci_platform_find_clk(hpriv, "aclk") ||
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!ahci_platform_find_clk(hpriv, "ref")) {
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dev_err(&dpriv->pdev->dev, "No system clocks specified\n");
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return -EINVAL;
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}
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/*
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* Fully reset the SATA AXI and ref clocks domain to ensure the state
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* machine is working from scratch especially if the reference clocks
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* source has been changed.
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*/
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ret = ahci_platform_assert_rsts(hpriv);
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if (ret) {
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dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n");
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return ret;
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}
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ret = ahci_platform_deassert_rsts(hpriv);
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if (ret) {
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dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n");
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return ret;
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}
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return 0;
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}
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static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)
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{
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struct ahci_dwc_host_priv *dpriv;
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struct ahci_host_priv *hpriv;
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dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL);
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if (!dpriv)
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return ERR_PTR(-ENOMEM);
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dpriv->pdev = pdev;
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dpriv->pdata = device_get_match_data(&pdev->dev);
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if (!dpriv->pdata)
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return ERR_PTR(-EINVAL);
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hpriv = ahci_platform_get_resources(pdev, dpriv->pdata->pflags);
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if (IS_ERR(hpriv))
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return hpriv;
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hpriv->flags |= dpriv->pdata->hflags;
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hpriv->plat_data = (void *)dpriv;
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return hpriv;
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}
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static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv)
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{
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unsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map;
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struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
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bool dev_mp, dev_cp, fbs_sup;
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unsigned int fbs_pmp;
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u32 param;
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int i;
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param = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R);
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dev_mp = !!(param & AHCI_DWC_HOST_DEV_MP);
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dev_cp = !!(param & AHCI_DWC_HOST_DEV_CP);
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fbs_sup = !!(param & AHCI_DWC_HOST_FBS_SUP);
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fbs_pmp = 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param);
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if (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) {
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dev_warn(&dpriv->pdev->dev, "MPS is unsupported\n");
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hpriv->saved_cap &= ~HOST_CAP_MPS;
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}
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if (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) {
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dev_warn(&dpriv->pdev->dev, "PMPn is limited up to %u ports\n",
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fbs_pmp);
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}
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for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
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if (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) {
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dev_warn(&dpriv->pdev->dev, "MPS incapable port %d\n", i);
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hpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP;
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}
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if (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) {
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dev_warn(&dpriv->pdev->dev, "CPD incapable port %d\n", i);
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hpriv->saved_port_cap[i] &= ~PORT_CMD_CPD;
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}
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if (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) {
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dev_warn(&dpriv->pdev->dev, "FBS incapable port %d\n", i);
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hpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP;
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}
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}
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}
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static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv)
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{
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struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
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unsigned long rate;
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struct clk *aclk;
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u32 cap, cap2;
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/* 1ms tick is generated only for the CCC or DevSleep features */
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cap = readl(hpriv->mmio + HOST_CAP);
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cap2 = readl(hpriv->mmio + HOST_CAP2);
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if (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS))
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return;
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/*
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* Tick is generated based on the AXI/AHB application clocks signal
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* so we need to be sure in the clock we are going to use.
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*/
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aclk = ahci_platform_find_clk(hpriv, "aclk");
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if (!aclk)
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return;
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/* 1ms timer interval is set as TIMV = AMBA_FREQ[MHZ] * 1000 */
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dpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
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dpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv);
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rate = clk_get_rate(aclk) / 1000UL;
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if (rate == dpriv->timv)
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return;
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dev_info(&dpriv->pdev->dev, "Update CCC/DevSlp timer for Fapp %lu MHz\n",
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rate / 1000UL);
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dpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate);
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writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
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}
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static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv)
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{
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struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
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struct device_node *child;
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void __iomem *port_mmio;
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u32 port, dmacr, ts;
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/*
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* Update the DMA Tx/Rx transaction sizes in accordance with the
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* platform setup. Note values exceeding maximal or minimal limits will
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* be automatically clamped. Also note the register isn't affected by
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* the HBA global reset so we can freely initialize it once until the
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* next system reset.
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*/
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for_each_child_of_node(dpriv->pdev->dev.of_node, child) {
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if (!of_device_is_available(child))
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continue;
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if (of_property_read_u32(child, "reg", &port)) {
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of_node_put(child);
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return -EINVAL;
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}
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port_mmio = __ahci_port_base(hpriv, port);
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dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR);
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if (!of_property_read_u32(child, "snps,tx-ts-max", &ts)) {
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ts = ilog2(ts);
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dmacr &= ~AHCI_DWC_PORT_TXTS_MASK;
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dmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts);
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}
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if (!of_property_read_u32(child, "snps,rx-ts-max", &ts)) {
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ts = ilog2(ts);
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dmacr &= ~AHCI_DWC_PORT_RXTS_MASK;
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dmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts);
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}
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writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR);
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dpriv->dmacr[port] = dmacr;
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}
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return 0;
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}
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static int ahci_dwc_init_host(struct ahci_host_priv *hpriv)
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{
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struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
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int rc;
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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if (dpriv->pdata->init) {
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rc = dpriv->pdata->init(hpriv);
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if (rc)
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goto err_disable_resources;
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}
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ahci_dwc_check_cap(hpriv);
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ahci_dwc_init_timer(hpriv);
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rc = ahci_dwc_init_dmacr(hpriv);
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if (rc)
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goto err_clear_platform;
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|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_clear_platform:
|
||
|
|
if (dpriv->pdata->clear)
|
||
|
|
dpriv->pdata->clear(hpriv);
|
||
|
|
|
||
|
|
err_disable_resources:
|
||
|
|
ahci_platform_disable_resources(hpriv);
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)
|
||
|
|
{
|
||
|
|
struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
|
||
|
|
unsigned long port_map = hpriv->port_map;
|
||
|
|
void __iomem *port_mmio;
|
||
|
|
int i, rc;
|
||
|
|
|
||
|
|
rc = ahci_platform_enable_resources(hpriv);
|
||
|
|
if (rc)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
if (dpriv->pdata->reinit) {
|
||
|
|
rc = dpriv->pdata->reinit(hpriv);
|
||
|
|
if (rc)
|
||
|
|
goto err_disable_resources;
|
||
|
|
}
|
||
|
|
|
||
|
|
writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
|
||
|
|
|
||
|
|
for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
|
||
|
|
port_mmio = __ahci_port_base(hpriv, i);
|
||
|
|
writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_disable_resources:
|
||
|
|
ahci_platform_disable_resources(hpriv);
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv)
|
||
|
|
{
|
||
|
|
struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
|
||
|
|
|
||
|
|
if (dpriv->pdata->clear)
|
||
|
|
dpriv->pdata->clear(hpriv);
|
||
|
|
|
||
|
|
ahci_platform_disable_resources(hpriv);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ahci_dwc_stop_host(struct ata_host *host)
|
||
|
|
{
|
||
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
||
|
|
|
||
|
|
ahci_dwc_clear_host(hpriv);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct ata_port_operations ahci_dwc_port_ops = {
|
||
|
|
.inherits = &ahci_platform_ops,
|
||
|
|
.host_stop = ahci_dwc_stop_host,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct ata_port_info ahci_dwc_port_info = {
|
||
|
|
.flags = AHCI_FLAG_COMMON,
|
||
|
|
.pio_mask = ATA_PIO4,
|
||
|
|
.udma_mask = ATA_UDMA6,
|
||
|
|
.port_ops = &ahci_dwc_port_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct scsi_host_template ahci_dwc_scsi_info = {
|
||
|
|
AHCI_SHT(DRV_NAME),
|
||
|
|
};
|
||
|
|
|
||
|
|
static int ahci_dwc_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct ahci_host_priv *hpriv;
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
hpriv = ahci_dwc_get_resources(pdev);
|
||
|
|
if (IS_ERR(hpriv))
|
||
|
|
return PTR_ERR(hpriv);
|
||
|
|
|
||
|
|
rc = ahci_dwc_init_host(hpriv);
|
||
|
|
if (rc)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
rc = ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info,
|
||
|
|
&ahci_dwc_scsi_info);
|
||
|
|
if (rc)
|
||
|
|
goto err_clear_host;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_clear_host:
|
||
|
|
ahci_dwc_clear_host(hpriv);
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ahci_dwc_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
||
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
rc = ahci_platform_suspend_host(dev);
|
||
|
|
if (rc)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
ahci_dwc_clear_host(hpriv);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ahci_dwc_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
||
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
rc = ahci_dwc_reinit_host(hpriv);
|
||
|
|
if (rc)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
return ahci_platform_resume_host(dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend,
|
||
|
|
ahci_dwc_resume);
|
||
|
|
|
||
|
|
static struct ahci_dwc_plat_data ahci_dwc_plat = {
|
||
|
|
.pflags = AHCI_PLATFORM_GET_RESETS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct ahci_dwc_plat_data ahci_bt1_plat = {
|
||
|
|
.pflags = AHCI_PLATFORM_GET_RESETS | AHCI_PLATFORM_RST_TRIGGER,
|
||
|
|
.init = ahci_bt1_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id ahci_dwc_of_match[] = {
|
||
|
|
{ .compatible = "snps,dwc-ahci", &ahci_dwc_plat },
|
||
|
|
{ .compatible = "snps,spear-ahci", &ahci_dwc_plat },
|
||
|
|
{ .compatible = "baikal,bt1-ahci", &ahci_bt1_plat },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver ahci_dwc_driver = {
|
||
|
|
.probe = ahci_dwc_probe,
|
||
|
|
.remove = ata_platform_remove_one,
|
||
|
|
.shutdown = ahci_platform_shutdown,
|
||
|
|
.driver = {
|
||
|
|
.name = DRV_NAME,
|
||
|
|
.of_match_table = ahci_dwc_of_match,
|
||
|
|
.pm = &ahci_dwc_pm_ops,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(ahci_dwc_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("DWC AHCI SATA platform driver");
|
||
|
|
MODULE_AUTHOR("Serge Semin <Sergey.Semin@baikalelectronics.ru>");
|
||
|
|
MODULE_LICENSE("GPL");
|