294 lines
8.7 KiB
C
294 lines
8.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
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*/
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#include "asm-generic/errno-base.h"
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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/* address offset of control registers */
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#define MPFS_CCC_PLL_CR 0x04u
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#define MPFS_CCC_REF_CR 0x08u
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#define MPFS_CCC_SSCG_2_CR 0x2Cu
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#define MPFS_CCC_POSTDIV01_CR 0x10u
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#define MPFS_CCC_POSTDIV23_CR 0x14u
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#define MPFS_CCC_FBDIV_SHIFT 0x00u
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#define MPFS_CCC_FBDIV_WIDTH 0x0Cu
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#define MPFS_CCC_POSTDIV0_SHIFT 0x08u
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#define MPFS_CCC_POSTDIV1_SHIFT 0x18u
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#define MPFS_CCC_POSTDIV2_SHIFT MPFS_CCC_POSTDIV0_SHIFT
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#define MPFS_CCC_POSTDIV3_SHIFT MPFS_CCC_POSTDIV1_SHIFT
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#define MPFS_CCC_POSTDIV_WIDTH 0x06u
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#define MPFS_CCC_REFCLK_SEL BIT(6)
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#define MPFS_CCC_REFDIV_SHIFT 0x08u
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#define MPFS_CCC_REFDIV_WIDTH 0x06u
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#define MPFS_CCC_FIXED_DIV 4
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#define MPFS_CCC_OUTPUTS_PER_PLL 4
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#define MPFS_CCC_REFS_PER_PLL 2
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struct mpfs_ccc_data {
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void __iomem **pll_base;
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struct device *dev;
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struct clk_hw_onecell_data hw_data;
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};
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struct mpfs_ccc_pll_hw_clock {
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void __iomem *base;
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const char *name;
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const struct clk_parent_data *parents;
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unsigned int id;
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u32 reg_offset;
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u32 shift;
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u32 width;
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u32 flags;
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struct clk_hw hw;
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struct clk_init_data init;
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};
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#define to_mpfs_ccc_clk(_hw) container_of(_hw, struct mpfs_ccc_pll_hw_clock, hw)
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/*
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* mpfs_ccc_lock prevents anything else from writing to a fabric ccc
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* while a software locked register is being written.
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*/
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static DEFINE_SPINLOCK(mpfs_ccc_lock);
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static const struct clk_parent_data mpfs_ccc_pll0_refs[] = {
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{ .fw_name = "pll0_ref0" },
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{ .fw_name = "pll0_ref1" },
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};
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static const struct clk_parent_data mpfs_ccc_pll1_refs[] = {
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{ .fw_name = "pll1_ref0" },
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{ .fw_name = "pll1_ref1" },
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};
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static unsigned long mpfs_ccc_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw);
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void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset;
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void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR;
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u32 mult, ref_div;
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mult = readl_relaxed(mult_addr) >> MPFS_CCC_FBDIV_SHIFT;
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mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH);
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ref_div = readl_relaxed(ref_div_addr) >> MPFS_CCC_REFDIV_SHIFT;
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ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH);
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return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV);
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}
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static u8 mpfs_ccc_pll_get_parent(struct clk_hw *hw)
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{
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struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw);
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void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR;
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return !!(readl_relaxed(pll_cr_addr) & MPFS_CCC_REFCLK_SEL);
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}
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static const struct clk_ops mpfs_ccc_pll_ops = {
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.recalc_rate = mpfs_ccc_pll_recalc_rate,
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.get_parent = mpfs_ccc_pll_get_parent,
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};
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#define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \
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.id = _id, \
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.shift = _shift, \
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.width = _width, \
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.reg_offset = _offset, \
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.flags = _flags, \
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.parents = _parents, \
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}
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static struct mpfs_ccc_pll_hw_clock mpfs_ccc_pll_clks[] = {
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CLK_CCC_PLL(CLK_CCC_PLL0, mpfs_ccc_pll0_refs, MPFS_CCC_FBDIV_SHIFT,
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MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR),
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CLK_CCC_PLL(CLK_CCC_PLL1, mpfs_ccc_pll1_refs, MPFS_CCC_FBDIV_SHIFT,
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MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR),
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};
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struct mpfs_ccc_out_hw_clock {
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struct clk_divider divider;
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struct clk_init_data init;
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unsigned int id;
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u32 reg_offset;
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};
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#define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \
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.id = _id, \
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.divider.shift = _shift, \
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.divider.width = _width, \
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.reg_offset = _offset, \
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.divider.flags = _flags, \
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.divider.lock = &mpfs_ccc_lock, \
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}
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static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll0out_clks[] = {
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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};
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static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll1out_clks[] = {
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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};
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static struct mpfs_ccc_out_hw_clock *mpfs_ccc_pllout_clks[] = {
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mpfs_ccc_pll0out_clks, mpfs_ccc_pll1out_clks
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};
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static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_clock *out_hws,
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unsigned int num_clks, struct mpfs_ccc_data *data,
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struct mpfs_ccc_pll_hw_clock *parent)
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{
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int ret;
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for (unsigned int i = 0; i < num_clks; i++) {
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struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
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char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i);
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if (!name)
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return -ENOMEM;
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out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
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out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
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out_hw->reg_offset;
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ret = devm_clk_hw_register(dev, &out_hw->divider.hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
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out_hw->id);
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data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
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}
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return 0;
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}
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#define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \
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(&(struct clk_init_data) { \
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.flags = _flags, \
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.name = _name, \
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.parent_data = _parents, \
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.num_parents = MPFS_CCC_REFS_PER_PLL, \
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.ops = _ops, \
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})
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static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clock *pll_hws,
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unsigned int num_clks, struct mpfs_ccc_data *data)
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{
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int ret;
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for (unsigned int i = 0; i < num_clks; i++) {
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struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
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pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u",
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strchrnul(dev->of_node->full_name, '@'), i);
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if (!pll_hw->name)
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return -ENOMEM;
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pll_hw->base = data->pll_base[i];
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pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,
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pll_hw->parents,
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&mpfs_ccc_pll_ops, 0);
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ret = devm_clk_hw_register(dev, &pll_hw->hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register ccc id: %d\n",
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pll_hw->id);
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data->hw_data.hws[pll_hw->id] = &pll_hw->hw;
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ret = mpfs_ccc_register_outputs(dev, mpfs_ccc_pllout_clks[i],
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MPFS_CCC_OUTPUTS_PER_PLL, data, pll_hw);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int mpfs_ccc_probe(struct platform_device *pdev)
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{
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struct mpfs_ccc_data *clk_data;
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void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)];
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unsigned int num_clks;
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int ret;
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num_clks = ARRAY_SIZE(mpfs_ccc_pll_clks) + ARRAY_SIZE(mpfs_ccc_pll0out_clks) +
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ARRAY_SIZE(mpfs_ccc_pll1out_clks);
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clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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pll_base[0] = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pll_base[0]))
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return PTR_ERR(pll_base[0]);
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pll_base[1] = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(pll_base[1]))
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return PTR_ERR(pll_base[1]);
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clk_data->pll_base = pll_base;
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clk_data->hw_data.num = num_clks;
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clk_data->dev = &pdev->dev;
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ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks,
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ARRAY_SIZE(mpfs_ccc_pll_clks), clk_data);
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if (ret)
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return ret;
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return devm_of_clk_add_hw_provider(clk_data->dev, of_clk_hw_onecell_get,
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&clk_data->hw_data);
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}
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static const struct of_device_id mpfs_ccc_of_match_table[] = {
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{ .compatible = "microchip,mpfs-ccc", },
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{}
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};
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MODULE_DEVICE_TABLE(of, mpfs_ccc_of_match_table);
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static struct platform_driver mpfs_ccc_driver = {
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.probe = mpfs_ccc_probe,
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.driver = {
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.name = "microchip-mpfs-ccc",
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.of_match_table = mpfs_ccc_of_match_table,
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},
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};
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static int __init clk_ccc_init(void)
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{
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return platform_driver_register(&mpfs_ccc_driver);
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}
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core_initcall(clk_ccc_init);
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static void __exit clk_ccc_exit(void)
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{
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platform_driver_unregister(&mpfs_ccc_driver);
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}
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module_exit(clk_ccc_exit);
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MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Conditioning Circuitry Driver");
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MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
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