95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2021 Linaro Ltd.
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* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
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* Author: Sam Protsenko <semen.protsenko@linaro.org>
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* Author: Dávid Virág <virag.david003@gmail.com>
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*
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* This file contains shared functions used by some arm64 Exynos SoCs,
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* such as Exynos7885 or Exynos850 to register and init CMUs.
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*/
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#include <linux/clk.h>
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#include <linux/of_address.h>
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#include "clk-exynos-arm64.h"
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/* Gate register bits */
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#define GATE_MANUAL BIT(20)
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#define GATE_ENABLE_HWACG BIT(28)
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/* Gate register offsets range */
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#define GATE_OFF_START 0x2000
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#define GATE_OFF_END 0x2fff
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/**
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* exynos_arm64_init_clocks - Set clocks initial configuration
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* @np: CMU device tree node with "reg" property (CMU addr)
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* @reg_offs: Register offsets array for clocks to init
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* @reg_offs_len: Number of register offsets in reg_offs array
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*
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* Set manual control mode for all gate clocks.
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*/
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static void __init exynos_arm64_init_clocks(struct device_node *np,
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const unsigned long *reg_offs, size_t reg_offs_len)
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{
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void __iomem *reg_base;
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size_t i;
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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for (i = 0; i < reg_offs_len; ++i) {
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void __iomem *reg = reg_base + reg_offs[i];
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u32 val;
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/* Modify only gate clock registers */
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if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
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continue;
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val = readl(reg);
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val |= GATE_MANUAL;
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val &= ~GATE_ENABLE_HWACG;
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writel(val, reg);
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}
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iounmap(reg_base);
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}
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/**
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* exynos_arm64_register_cmu - Register specified Exynos CMU domain
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* @dev: Device object; may be NULL if this function is not being
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* called from platform driver probe function
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* @np: CMU device tree node
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* @cmu: CMU data
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*
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* Register specified CMU domain, which includes next steps:
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*
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* 1. Enable parent clock of @cmu CMU
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* 2. Set initial registers configuration for @cmu CMU clocks
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* 3. Register @cmu CMU clocks using Samsung clock framework API
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*/
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void __init exynos_arm64_register_cmu(struct device *dev,
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struct device_node *np, const struct samsung_cmu_info *cmu)
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{
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/* Keep CMU parent clock running (needed for CMU registers access) */
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if (cmu->clk_name) {
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struct clk *parent_clk;
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if (dev)
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parent_clk = clk_get(dev, cmu->clk_name);
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else
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parent_clk = of_clk_get_by_name(np, cmu->clk_name);
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if (IS_ERR(parent_clk)) {
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pr_err("%s: could not find bus clock %s; err = %ld\n",
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__func__, cmu->clk_name, PTR_ERR(parent_clk));
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} else {
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clk_prepare_enable(parent_clk);
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}
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}
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exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
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samsung_cmu_register_one(np, cmu);
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}
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