307 lines
8.0 KiB
C
307 lines
8.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Padmavathi Venna <padma.v@samsung.com>
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*
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* Common Clock Framework support for Audio Subsystem Clock Controller.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <dt-bindings/clock/exynos-audss-clk.h>
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static DEFINE_SPINLOCK(lock);
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static void __iomem *reg_base;
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static struct clk_hw_onecell_data *clk_data;
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/*
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* On Exynos5420 this will be a clock which has to be enabled before any
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* access to audss registers. Typically a child of EPLL.
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*
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* On other platforms this will be -ENODEV.
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*/
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static struct clk *epll;
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#define ASS_CLK_SRC 0x0
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_GATE 0x8
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static unsigned long reg_save[][2] = {
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{ ASS_CLK_SRC, 0 },
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{ ASS_CLK_DIV, 0 },
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{ ASS_CLK_GATE, 0 },
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};
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static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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reg_save[i][1] = readl(reg_base + reg_save[i][0]);
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return 0;
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}
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static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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writel(reg_save[i][1], reg_base + reg_save[i][0]);
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return 0;
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}
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struct exynos_audss_clk_drvdata {
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unsigned int has_adma_clk:1;
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unsigned int has_mst_clk:1;
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unsigned int enable_epll:1;
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unsigned int num_clks;
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};
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static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
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.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
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.enable_epll = 1,
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};
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static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
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.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
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.has_mst_clk = 1,
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};
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static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
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.num_clks = EXYNOS_AUDSS_MAX_CLKS,
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.has_adma_clk = 1,
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.enable_epll = 1,
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};
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static const struct of_device_id exynos_audss_clk_of_match[] = {
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{
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.compatible = "samsung,exynos4210-audss-clock",
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.data = &exynos4210_drvdata,
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}, {
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.compatible = "samsung,exynos5250-audss-clock",
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.data = &exynos4210_drvdata,
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}, {
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.compatible = "samsung,exynos5410-audss-clock",
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.data = &exynos5410_drvdata,
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}, {
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.compatible = "samsung,exynos5420-audss-clock",
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.data = &exynos5420_drvdata,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
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static void exynos_audss_clk_teardown(void)
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{
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int i;
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for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
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if (!IS_ERR(clk_data->hws[i]))
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clk_hw_unregister_mux(clk_data->hws[i]);
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}
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for (; i < EXYNOS_SRP_CLK; i++) {
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if (!IS_ERR(clk_data->hws[i]))
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clk_hw_unregister_divider(clk_data->hws[i]);
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}
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for (; i < clk_data->num; i++) {
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if (!IS_ERR(clk_data->hws[i]))
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clk_hw_unregister_gate(clk_data->hws[i]);
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}
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}
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/* register exynos_audss clocks */
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static int exynos_audss_clk_probe(struct platform_device *pdev)
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{
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const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
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const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
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const char *sclk_pcm_p = "sclk_pcm0";
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struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
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const struct exynos_audss_clk_drvdata *variant;
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struct clk_hw **clk_table;
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struct device *dev = &pdev->dev;
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int i, ret = 0;
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variant = of_device_get_match_data(&pdev->dev);
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if (!variant)
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return -EINVAL;
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reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg_base))
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return PTR_ERR(reg_base);
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epll = ERR_PTR(-ENODEV);
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clk_data = devm_kzalloc(dev,
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struct_size(clk_data, hws,
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EXYNOS_AUDSS_MAX_CLKS),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->num = variant->num_clks;
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clk_table = clk_data->hws;
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pll_ref = devm_clk_get(dev, "pll_ref");
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pll_in = devm_clk_get(dev, "pll_in");
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if (!IS_ERR(pll_ref))
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mout_audss_p[0] = __clk_get_name(pll_ref);
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if (!IS_ERR(pll_in)) {
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mout_audss_p[1] = __clk_get_name(pll_in);
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if (variant->enable_epll) {
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epll = pll_in;
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ret = clk_prepare_enable(epll);
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if (ret) {
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dev_err(dev,
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"failed to prepare the epll clock\n");
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return ret;
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}
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}
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}
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/*
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* Enable runtime PM here to allow the clock core using runtime PM
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* for the registered clocks. Additionally, we increase the runtime
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* PM usage count before registering the clocks, to prevent the
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* clock core from runtime suspending the device.
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*/
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pm_runtime_get_noresume(dev);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
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mout_audss_p, ARRAY_SIZE(mout_audss_p),
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CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
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cdclk = devm_clk_get(dev, "cdclk");
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sclk_audio = devm_clk_get(dev, "sclk_audio");
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if (!IS_ERR(cdclk))
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mout_i2s_p[1] = __clk_get_name(cdclk);
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if (!IS_ERR(sclk_audio))
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mout_i2s_p[2] = __clk_get_name(sclk_audio);
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clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
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mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
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CLK_SET_RATE_NO_REPARENT,
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reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
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clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
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"mout_audss", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
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clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
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"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
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clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
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"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
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&lock);
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clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
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"dout_srp", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 0, 0, &lock);
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clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
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"dout_aud_bus", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 2, 0, &lock);
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clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
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"dout_i2s", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 3, 0, &lock);
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clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
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"sclk_pcm", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 4, 0, &lock);
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sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
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if (!IS_ERR(sclk_pcm_in))
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sclk_pcm_p = __clk_get_name(sclk_pcm_in);
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clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
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sclk_pcm_p, CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 5, 0, &lock);
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if (variant->has_adma_clk) {
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clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
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"dout_srp", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 9, 0, &lock);
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}
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for (i = 0; i < clk_data->num; i++) {
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if (IS_ERR(clk_table[i])) {
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dev_err(dev, "failed to register clock %d\n", i);
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ret = PTR_ERR(clk_table[i]);
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goto unregister;
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}
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}
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ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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clk_data);
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if (ret) {
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dev_err(dev, "failed to add clock provider\n");
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goto unregister;
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}
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pm_runtime_put_sync(dev);
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return 0;
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unregister:
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exynos_audss_clk_teardown();
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pm_runtime_put_sync(dev);
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pm_runtime_disable(dev);
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if (!IS_ERR(epll))
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clk_disable_unprepare(epll);
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return ret;
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}
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static int exynos_audss_clk_remove(struct platform_device *pdev)
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{
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of_clk_del_provider(pdev->dev.of_node);
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exynos_audss_clk_teardown();
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pm_runtime_disable(&pdev->dev);
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if (!IS_ERR(epll))
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clk_disable_unprepare(epll);
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return 0;
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}
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static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
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SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
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NULL)
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SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static struct platform_driver exynos_audss_clk_driver = {
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.driver = {
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.name = "exynos-audss-clk",
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.of_match_table = exynos_audss_clk_of_match,
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.pm = &exynos_audss_clk_pm_ops,
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},
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.probe = exynos_audss_clk_probe,
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.remove = exynos_audss_clk_remove,
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};
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module_platform_driver(exynos_audss_clk_driver);
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MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
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MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:exynos-audss-clk");
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