583 lines
14 KiB
C
583 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 MaxLinear, Inc.
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* Copyright (C) 2020 Intel Corporation.
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* Zhu Yixin <yzhu@maxlinear.com>
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* Rahul Tanwar <rtanwar@maxlinear.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include "clk-cgu.h"
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#define GATE_HW_REG_STAT(reg) ((reg) + 0x0)
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#define GATE_HW_REG_EN(reg) ((reg) + 0x4)
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#define GATE_HW_REG_DIS(reg) ((reg) + 0x8)
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#define MAX_DDIV_REG 8
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#define MAX_DIVIDER_VAL 64
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#define to_lgm_clk_mux(_hw) container_of(_hw, struct lgm_clk_mux, hw)
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#define to_lgm_clk_divider(_hw) container_of(_hw, struct lgm_clk_divider, hw)
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#define to_lgm_clk_gate(_hw) container_of(_hw, struct lgm_clk_gate, hw)
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#define to_lgm_clk_ddiv(_hw) container_of(_hw, struct lgm_clk_ddiv, hw)
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static struct clk_hw *lgm_clk_register_fixed(struct lgm_clk_provider *ctx,
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const struct lgm_clk_branch *list)
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{
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if (list->div_flags & CLOCK_FLAG_VAL_INIT)
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lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift,
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list->div_width, list->div_val);
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return clk_hw_register_fixed_rate(NULL, list->name,
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list->parent_data[0].name,
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list->flags, list->mux_flags);
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}
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static u8 lgm_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct lgm_clk_mux *mux = to_lgm_clk_mux(hw);
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u32 val;
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if (mux->flags & MUX_CLK_SW)
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val = mux->reg;
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else
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val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift,
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mux->width);
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return clk_mux_val_to_index(hw, NULL, mux->flags, val);
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}
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static int lgm_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct lgm_clk_mux *mux = to_lgm_clk_mux(hw);
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u32 val;
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val = clk_mux_index_to_val(NULL, mux->flags, index);
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if (mux->flags & MUX_CLK_SW)
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mux->reg = val;
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else
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lgm_set_clk_val(mux->membase, mux->reg, mux->shift,
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mux->width, val);
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return 0;
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}
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static int lgm_clk_mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct lgm_clk_mux *mux = to_lgm_clk_mux(hw);
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return clk_mux_determine_rate_flags(hw, req, mux->flags);
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}
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static const struct clk_ops lgm_clk_mux_ops = {
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.get_parent = lgm_clk_mux_get_parent,
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.set_parent = lgm_clk_mux_set_parent,
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.determine_rate = lgm_clk_mux_determine_rate,
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};
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static struct clk_hw *
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lgm_clk_register_mux(struct lgm_clk_provider *ctx,
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const struct lgm_clk_branch *list)
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{
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unsigned long cflags = list->mux_flags;
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struct device *dev = ctx->dev;
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u8 shift = list->mux_shift;
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u8 width = list->mux_width;
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struct clk_init_data init = {};
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struct lgm_clk_mux *mux;
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u32 reg = list->mux_off;
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struct clk_hw *hw;
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int ret;
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = list->name;
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init.ops = &lgm_clk_mux_ops;
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init.flags = list->flags;
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init.parent_data = list->parent_data;
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init.num_parents = list->num_parents;
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mux->membase = ctx->membase;
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mux->reg = reg;
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mux->shift = shift;
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mux->width = width;
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mux->flags = cflags;
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mux->hw.init = &init;
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hw = &mux->hw;
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ret = devm_clk_hw_register(dev, hw);
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if (ret)
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return ERR_PTR(ret);
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if (cflags & CLOCK_FLAG_VAL_INIT)
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lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val);
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return hw;
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}
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static unsigned long
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lgm_clk_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct lgm_clk_divider *divider = to_lgm_clk_divider(hw);
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unsigned int val;
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val = lgm_get_clk_val(divider->membase, divider->reg,
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divider->shift, divider->width);
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return divider_recalc_rate(hw, parent_rate, val, divider->table,
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divider->flags, divider->width);
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}
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static long
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lgm_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct lgm_clk_divider *divider = to_lgm_clk_divider(hw);
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return divider_round_rate(hw, rate, prate, divider->table,
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divider->width, divider->flags);
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}
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static int
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lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct lgm_clk_divider *divider = to_lgm_clk_divider(hw);
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int value;
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value = divider_get_val(rate, prate, divider->table,
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divider->width, divider->flags);
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if (value < 0)
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return value;
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lgm_set_clk_val(divider->membase, divider->reg,
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divider->shift, divider->width, value);
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return 0;
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}
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static int lgm_clk_divider_enable_disable(struct clk_hw *hw, int enable)
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{
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struct lgm_clk_divider *div = to_lgm_clk_divider(hw);
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if (div->flags != DIV_CLK_NO_MASK)
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lgm_set_clk_val(div->membase, div->reg, div->shift_gate,
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div->width_gate, enable);
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return 0;
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}
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static int lgm_clk_divider_enable(struct clk_hw *hw)
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{
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return lgm_clk_divider_enable_disable(hw, 1);
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}
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static void lgm_clk_divider_disable(struct clk_hw *hw)
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{
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lgm_clk_divider_enable_disable(hw, 0);
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}
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static const struct clk_ops lgm_clk_divider_ops = {
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.recalc_rate = lgm_clk_divider_recalc_rate,
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.round_rate = lgm_clk_divider_round_rate,
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.set_rate = lgm_clk_divider_set_rate,
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.enable = lgm_clk_divider_enable,
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.disable = lgm_clk_divider_disable,
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};
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static struct clk_hw *
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lgm_clk_register_divider(struct lgm_clk_provider *ctx,
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const struct lgm_clk_branch *list)
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{
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unsigned long cflags = list->div_flags;
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struct device *dev = ctx->dev;
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struct lgm_clk_divider *div;
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struct clk_init_data init = {};
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u8 shift = list->div_shift;
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u8 width = list->div_width;
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u8 shift_gate = list->div_shift_gate;
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u8 width_gate = list->div_width_gate;
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u32 reg = list->div_off;
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struct clk_hw *hw;
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int ret;
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div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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init.name = list->name;
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init.ops = &lgm_clk_divider_ops;
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init.flags = list->flags;
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init.parent_data = list->parent_data;
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init.num_parents = 1;
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div->membase = ctx->membase;
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->shift_gate = shift_gate;
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div->width_gate = width_gate;
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div->flags = cflags;
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div->table = list->div_table;
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div->hw.init = &init;
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hw = &div->hw;
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ret = devm_clk_hw_register(dev, hw);
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if (ret)
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return ERR_PTR(ret);
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if (cflags & CLOCK_FLAG_VAL_INIT)
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lgm_set_clk_val(div->membase, reg, shift, width, list->div_val);
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return hw;
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}
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static struct clk_hw *
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lgm_clk_register_fixed_factor(struct lgm_clk_provider *ctx,
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const struct lgm_clk_branch *list)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
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list->parent_data[0].name, list->flags,
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list->mult, list->div);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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if (list->div_flags & CLOCK_FLAG_VAL_INIT)
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lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift,
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list->div_width, list->div_val);
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return hw;
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}
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static int lgm_clk_gate_enable(struct clk_hw *hw)
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{
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struct lgm_clk_gate *gate = to_lgm_clk_gate(hw);
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unsigned int reg;
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reg = GATE_HW_REG_EN(gate->reg);
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lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1);
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return 0;
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}
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static void lgm_clk_gate_disable(struct clk_hw *hw)
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{
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struct lgm_clk_gate *gate = to_lgm_clk_gate(hw);
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unsigned int reg;
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reg = GATE_HW_REG_DIS(gate->reg);
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lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1);
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}
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static int lgm_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct lgm_clk_gate *gate = to_lgm_clk_gate(hw);
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unsigned int reg, ret;
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reg = GATE_HW_REG_STAT(gate->reg);
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ret = lgm_get_clk_val(gate->membase, reg, gate->shift, 1);
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return ret;
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}
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static const struct clk_ops lgm_clk_gate_ops = {
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.enable = lgm_clk_gate_enable,
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.disable = lgm_clk_gate_disable,
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.is_enabled = lgm_clk_gate_is_enabled,
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};
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static struct clk_hw *
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lgm_clk_register_gate(struct lgm_clk_provider *ctx,
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const struct lgm_clk_branch *list)
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{
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unsigned long cflags = list->gate_flags;
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const char *pname = list->parent_data[0].name;
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struct device *dev = ctx->dev;
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u8 shift = list->gate_shift;
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struct clk_init_data init = {};
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struct lgm_clk_gate *gate;
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u32 reg = list->gate_off;
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struct clk_hw *hw;
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int ret;
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gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = list->name;
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init.ops = &lgm_clk_gate_ops;
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init.flags = list->flags;
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init.parent_names = pname ? &pname : NULL;
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init.num_parents = pname ? 1 : 0;
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gate->membase = ctx->membase;
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gate->reg = reg;
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gate->shift = shift;
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gate->flags = cflags;
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gate->hw.init = &init;
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hw = &gate->hw;
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ret = devm_clk_hw_register(dev, hw);
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if (ret)
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return ERR_PTR(ret);
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if (cflags & CLOCK_FLAG_VAL_INIT) {
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lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val);
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}
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return hw;
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}
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int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
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const struct lgm_clk_branch *list,
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unsigned int nr_clk)
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{
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struct clk_hw *hw;
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unsigned int idx;
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for (idx = 0; idx < nr_clk; idx++, list++) {
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switch (list->type) {
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case CLK_TYPE_FIXED:
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hw = lgm_clk_register_fixed(ctx, list);
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break;
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case CLK_TYPE_MUX:
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hw = lgm_clk_register_mux(ctx, list);
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break;
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case CLK_TYPE_DIVIDER:
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hw = lgm_clk_register_divider(ctx, list);
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break;
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case CLK_TYPE_FIXED_FACTOR:
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hw = lgm_clk_register_fixed_factor(ctx, list);
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break;
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case CLK_TYPE_GATE:
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if (list->gate_flags & GATE_CLK_HW) {
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hw = lgm_clk_register_gate(ctx, list);
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} else {
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/*
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||
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* GATE_CLKs can be controlled either from
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||
|
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* CGU clk driver i.e. this driver or directly
|
||
|
|
* from power management driver/daemon. It is
|
||
|
|
* dependent on the power policy/profile requirements
|
||
|
|
* of the end product. To override control of gate
|
||
|
|
* clks from this driver, provide NULL for this index
|
||
|
|
* of gate clk provider.
|
||
|
|
*/
|
||
|
|
hw = NULL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
dev_err(ctx->dev, "invalid clk type\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (IS_ERR(hw)) {
|
||
|
|
dev_err(ctx->dev,
|
||
|
|
"register clk: %s, type: %u failed!\n",
|
||
|
|
list->name, list->type);
|
||
|
|
return -EIO;
|
||
|
|
}
|
||
|
|
ctx->clk_data.hws[list->id] = hw;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static unsigned long
|
||
|
|
lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||
|
|
{
|
||
|
|
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
|
||
|
|
unsigned int div0, div1, exdiv;
|
||
|
|
u64 prate;
|
||
|
|
|
||
|
|
div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
|
||
|
|
ddiv->shift0, ddiv->width0) + 1;
|
||
|
|
div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
|
||
|
|
ddiv->shift1, ddiv->width1) + 1;
|
||
|
|
exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg,
|
||
|
|
ddiv->shift2, ddiv->width2);
|
||
|
|
prate = (u64)parent_rate;
|
||
|
|
do_div(prate, div0);
|
||
|
|
do_div(prate, div1);
|
||
|
|
|
||
|
|
if (exdiv) {
|
||
|
|
do_div(prate, ddiv->div);
|
||
|
|
prate *= ddiv->mult;
|
||
|
|
}
|
||
|
|
|
||
|
|
return prate;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int lgm_clk_ddiv_enable(struct clk_hw *hw)
|
||
|
|
{
|
||
|
|
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
|
||
|
|
|
||
|
|
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate,
|
||
|
|
ddiv->width_gate, 1);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void lgm_clk_ddiv_disable(struct clk_hw *hw)
|
||
|
|
{
|
||
|
|
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
|
||
|
|
|
||
|
|
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate,
|
||
|
|
ddiv->width_gate, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
lgm_clk_get_ddiv_val(u32 div, u32 *ddiv1, u32 *ddiv2)
|
||
|
|
{
|
||
|
|
u32 idx, temp;
|
||
|
|
|
||
|
|
*ddiv1 = 1;
|
||
|
|
*ddiv2 = 1;
|
||
|
|
|
||
|
|
if (div > MAX_DIVIDER_VAL)
|
||
|
|
div = MAX_DIVIDER_VAL;
|
||
|
|
|
||
|
|
if (div > 1) {
|
||
|
|
for (idx = 2; idx <= MAX_DDIV_REG; idx++) {
|
||
|
|
temp = DIV_ROUND_UP_ULL((u64)div, idx);
|
||
|
|
if (div % idx == 0 && temp <= MAX_DDIV_REG)
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (idx > MAX_DDIV_REG)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
*ddiv1 = temp;
|
||
|
|
*ddiv2 = idx;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
lgm_clk_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
|
||
|
|
unsigned long prate)
|
||
|
|
{
|
||
|
|
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
|
||
|
|
u32 div, ddiv1, ddiv2;
|
||
|
|
|
||
|
|
div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
|
||
|
|
|
||
|
|
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
|
||
|
|
div = DIV_ROUND_CLOSEST_ULL((u64)div, 5);
|
||
|
|
div = div * 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (div <= 0)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift0, ddiv->width0,
|
||
|
|
ddiv1 - 1);
|
||
|
|
|
||
|
|
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift1, ddiv->width1,
|
||
|
|
ddiv2 - 1);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static long
|
||
|
|
lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
|
||
|
|
unsigned long *prate)
|
||
|
|
{
|
||
|
|
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
|
||
|
|
u32 div, ddiv1, ddiv2;
|
||
|
|
u64 rate64;
|
||
|
|
|
||
|
|
div = DIV_ROUND_CLOSEST_ULL((u64)*prate, rate);
|
||
|
|
|
||
|
|
/* if predivide bit is enabled, modify div by factor of 2.5 */
|
||
|
|
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
|
||
|
|
div = div * 2;
|
||
|
|
div = DIV_ROUND_CLOSEST_ULL((u64)div, 5);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (div <= 0)
|
||
|
|
return *prate;
|
||
|
|
|
||
|
|
if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2) != 0)
|
||
|
|
if (lgm_clk_get_ddiv_val(div + 1, &ddiv1, &ddiv2) != 0)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
rate64 = *prate;
|
||
|
|
do_div(rate64, ddiv1);
|
||
|
|
do_div(rate64, ddiv2);
|
||
|
|
|
||
|
|
/* if predivide bit is enabled, modify rounded rate by factor of 2.5 */
|
||
|
|
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
|
||
|
|
rate64 = rate64 * 2;
|
||
|
|
rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5);
|
||
|
|
}
|
||
|
|
|
||
|
|
return rate64;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct clk_ops lgm_clk_ddiv_ops = {
|
||
|
|
.recalc_rate = lgm_clk_ddiv_recalc_rate,
|
||
|
|
.enable = lgm_clk_ddiv_enable,
|
||
|
|
.disable = lgm_clk_ddiv_disable,
|
||
|
|
.set_rate = lgm_clk_ddiv_set_rate,
|
||
|
|
.round_rate = lgm_clk_ddiv_round_rate,
|
||
|
|
};
|
||
|
|
|
||
|
|
int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
|
||
|
|
const struct lgm_clk_ddiv_data *list,
|
||
|
|
unsigned int nr_clk)
|
||
|
|
{
|
||
|
|
struct device *dev = ctx->dev;
|
||
|
|
struct clk_hw *hw;
|
||
|
|
unsigned int idx;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||
|
|
struct clk_init_data init = {};
|
||
|
|
struct lgm_clk_ddiv *ddiv;
|
||
|
|
|
||
|
|
ddiv = devm_kzalloc(dev, sizeof(*ddiv), GFP_KERNEL);
|
||
|
|
if (!ddiv)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
init.name = list->name;
|
||
|
|
init.ops = &lgm_clk_ddiv_ops;
|
||
|
|
init.flags = list->flags;
|
||
|
|
init.parent_data = list->parent_data;
|
||
|
|
init.num_parents = 1;
|
||
|
|
|
||
|
|
ddiv->membase = ctx->membase;
|
||
|
|
ddiv->reg = list->reg;
|
||
|
|
ddiv->shift0 = list->shift0;
|
||
|
|
ddiv->width0 = list->width0;
|
||
|
|
ddiv->shift1 = list->shift1;
|
||
|
|
ddiv->width1 = list->width1;
|
||
|
|
ddiv->shift_gate = list->shift_gate;
|
||
|
|
ddiv->width_gate = list->width_gate;
|
||
|
|
ddiv->shift2 = list->ex_shift;
|
||
|
|
ddiv->width2 = list->ex_width;
|
||
|
|
ddiv->flags = list->div_flags;
|
||
|
|
ddiv->mult = 2;
|
||
|
|
ddiv->div = 5;
|
||
|
|
ddiv->hw.init = &init;
|
||
|
|
|
||
|
|
hw = &ddiv->hw;
|
||
|
|
ret = devm_clk_hw_register(dev, hw);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "register clk: %s failed!\n", list->name);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
ctx->clk_data.hws[list->id] = hw;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|