99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (C) 2021 Marvell. */
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#include <linux/soc/marvell/octeontx2/asm.h>
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#include "otx2_cptpf.h"
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#include "otx2_cptvf.h"
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#include "otx2_cptlf.h"
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#include "cn10k_cpt.h"
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static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
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struct otx2_cptlf_info *lf);
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static struct cpt_hw_ops otx2_hw_ops = {
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.send_cmd = otx2_cpt_send_cmd,
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.cpt_get_compcode = otx2_cpt_get_compcode,
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.cpt_get_uc_compcode = otx2_cpt_get_uc_compcode,
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};
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static struct cpt_hw_ops cn10k_hw_ops = {
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.send_cmd = cn10k_cpt_send_cmd,
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.cpt_get_compcode = cn10k_cpt_get_compcode,
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.cpt_get_uc_compcode = cn10k_cpt_get_uc_compcode,
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};
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static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
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struct otx2_cptlf_info *lf)
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{
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void __iomem *lmtline = lf->lmtline;
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u64 val = (lf->slot & 0x7FF);
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u64 tar_addr = 0;
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/* tar_addr<6:4> = Size of first LMTST - 1 in units of 128b. */
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tar_addr |= (__force u64)lf->ioreg |
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(((OTX2_CPT_INST_SIZE/16) - 1) & 0x7) << 4;
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/*
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* Make sure memory areas pointed in CPT_INST_S
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* are flushed before the instruction is sent to CPT
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*/
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dma_wmb();
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/* Copy CPT command to LMTLINE */
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memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
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cn10k_lmt_flush(val, tar_addr);
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}
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int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)
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{
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struct pci_dev *pdev = cptpf->pdev;
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resource_size_t size;
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u64 lmt_base;
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if (!test_bit(CN10K_LMTST, &cptpf->cap_flag)) {
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cptpf->lfs.ops = &otx2_hw_ops;
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return 0;
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}
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cptpf->lfs.ops = &cn10k_hw_ops;
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lmt_base = readq(cptpf->reg_base + RVU_PF_LMTLINE_ADDR);
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if (!lmt_base) {
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dev_err(&pdev->dev, "PF LMTLINE address not configured\n");
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return -ENOMEM;
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}
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size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
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size -= ((1 + cptpf->max_vfs) * MBOX_SIZE);
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cptpf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, lmt_base, size);
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if (!cptpf->lfs.lmt_base) {
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dev_err(&pdev->dev,
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"Mapping of PF LMTLINE address failed\n");
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return -ENOMEM;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(cn10k_cptpf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT);
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int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)
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{
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struct pci_dev *pdev = cptvf->pdev;
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resource_size_t offset, size;
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if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) {
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cptvf->lfs.ops = &otx2_hw_ops;
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return 0;
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}
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cptvf->lfs.ops = &cn10k_hw_ops;
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offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
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size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
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/* Map VF LMILINE region */
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cptvf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, offset, size);
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if (!cptvf->lfs.lmt_base) {
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dev_err(&pdev->dev, "Unable to map BAR4\n");
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return -ENOMEM;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(cn10k_cptvf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT);
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