380 lines
9.3 KiB
C
380 lines
9.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AES XCBC routines supporting the Power 7+ Nest Accelerators driver
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*
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* Copyright (C) 2011-2012 International Business Machines Inc.
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*
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* Author: Kent Yoder <yoder1@us.ibm.com>
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*/
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#include <crypto/internal/hash.h>
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#include <crypto/aes.h>
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#include <crypto/algapi.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/crypto.h>
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#include <asm/vio.h>
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#include "nx_csbcpb.h"
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#include "nx.h"
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struct xcbc_state {
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u8 state[AES_BLOCK_SIZE];
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unsigned int count;
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u8 buffer[AES_BLOCK_SIZE];
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};
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static int nx_xcbc_set_key(struct crypto_shash *desc,
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const u8 *in_key,
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unsigned int key_len)
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{
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struct nx_crypto_ctx *nx_ctx = crypto_shash_ctx(desc);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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switch (key_len) {
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case AES_KEYSIZE_128:
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nx_ctx->ap = &nx_ctx->props[NX_PROPS_AES_128];
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break;
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default:
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return -EINVAL;
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}
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memcpy(csbcpb->cpb.aes_xcbc.key, in_key, key_len);
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return 0;
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}
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/*
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* Based on RFC 3566, for a zero-length message:
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*
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* n = 1
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* K1 = E(K, 0x01010101010101010101010101010101)
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* K3 = E(K, 0x03030303030303030303030303030303)
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* E[0] = 0x00000000000000000000000000000000
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* M[1] = 0x80000000000000000000000000000000 (0 length message with padding)
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* E[1] = (K1, M[1] ^ E[0] ^ K3)
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* Tag = M[1]
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*/
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static int nx_xcbc_empty(struct shash_desc *desc, u8 *out)
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{
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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struct nx_sg *in_sg, *out_sg;
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u8 keys[2][AES_BLOCK_SIZE];
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u8 key[32];
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int rc = 0;
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int len;
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/* Change to ECB mode */
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csbcpb->cpb.hdr.mode = NX_MODE_AES_ECB;
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memcpy(key, csbcpb->cpb.aes_xcbc.key, AES_BLOCK_SIZE);
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memcpy(csbcpb->cpb.aes_ecb.key, key, AES_BLOCK_SIZE);
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NX_CPB_FDM(csbcpb) |= NX_FDM_ENDE_ENCRYPT;
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/* K1 and K3 base patterns */
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memset(keys[0], 0x01, sizeof(keys[0]));
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memset(keys[1], 0x03, sizeof(keys[1]));
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len = sizeof(keys);
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/* Generate K1 and K3 encrypting the patterns */
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in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) keys, &len,
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nx_ctx->ap->sglen);
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if (len != sizeof(keys))
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return -EINVAL;
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out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *) keys, &len,
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nx_ctx->ap->sglen);
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if (len != sizeof(keys))
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return -EINVAL;
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->aes_ops));
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/* XOr K3 with the padding for a 0 length message */
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keys[1][0] ^= 0x80;
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len = sizeof(keys[1]);
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/* Encrypt the final result */
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memcpy(csbcpb->cpb.aes_ecb.key, keys[0], AES_BLOCK_SIZE);
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in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) keys[1], &len,
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nx_ctx->ap->sglen);
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if (len != sizeof(keys[1]))
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return -EINVAL;
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len = AES_BLOCK_SIZE;
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out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len,
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nx_ctx->ap->sglen);
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if (len != AES_BLOCK_SIZE)
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return -EINVAL;
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->aes_ops));
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out:
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/* Restore XCBC mode */
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csbcpb->cpb.hdr.mode = NX_MODE_AES_XCBC_MAC;
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memcpy(csbcpb->cpb.aes_xcbc.key, key, AES_BLOCK_SIZE);
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_ENDE_ENCRYPT;
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return rc;
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}
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static int nx_crypto_ctx_aes_xcbc_init2(struct crypto_tfm *tfm)
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{
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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int err;
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err = nx_crypto_ctx_aes_xcbc_init(tfm);
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if (err)
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return err;
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nx_ctx_init(nx_ctx, HCOP_FC_AES);
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NX_CPB_SET_KEY_SIZE(csbcpb, NX_KS_AES_128);
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csbcpb->cpb.hdr.mode = NX_MODE_AES_XCBC_MAC;
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return 0;
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}
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static int nx_xcbc_init(struct shash_desc *desc)
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{
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struct xcbc_state *sctx = shash_desc_ctx(desc);
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memset(sctx, 0, sizeof *sctx);
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return 0;
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}
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static int nx_xcbc_update(struct shash_desc *desc,
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const u8 *data,
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unsigned int len)
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{
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struct xcbc_state *sctx = shash_desc_ctx(desc);
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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struct nx_sg *in_sg;
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struct nx_sg *out_sg;
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u32 to_process = 0, leftover, total;
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unsigned int max_sg_len;
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unsigned long irq_flags;
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int rc = 0;
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int data_len;
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spin_lock_irqsave(&nx_ctx->lock, irq_flags);
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total = sctx->count + len;
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/* 2 cases for total data len:
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* 1: <= AES_BLOCK_SIZE: copy into state, return 0
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* 2: > AES_BLOCK_SIZE: process X blocks, copy in leftover
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*/
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if (total <= AES_BLOCK_SIZE) {
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memcpy(sctx->buffer + sctx->count, data, len);
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sctx->count += len;
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goto out;
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}
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in_sg = nx_ctx->in_sg;
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max_sg_len = min_t(u64, nx_driver.of.max_sg_len/sizeof(struct nx_sg),
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nx_ctx->ap->sglen);
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max_sg_len = min_t(u64, max_sg_len,
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nx_ctx->ap->databytelen/NX_PAGE_SIZE);
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data_len = AES_BLOCK_SIZE;
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out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
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&len, nx_ctx->ap->sglen);
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if (data_len != AES_BLOCK_SIZE) {
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rc = -EINVAL;
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goto out;
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}
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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do {
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to_process = total - to_process;
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to_process = to_process & ~(AES_BLOCK_SIZE - 1);
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leftover = total - to_process;
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/* the hardware will not accept a 0 byte operation for this
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* algorithm and the operation MUST be finalized to be correct.
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* So if we happen to get an update that falls on a block sized
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* boundary, we must save off the last block to finalize with
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* later. */
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if (!leftover) {
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to_process -= AES_BLOCK_SIZE;
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leftover = AES_BLOCK_SIZE;
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}
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if (sctx->count) {
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data_len = sctx->count;
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in_sg = nx_build_sg_list(nx_ctx->in_sg,
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(u8 *) sctx->buffer,
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&data_len,
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max_sg_len);
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if (data_len != sctx->count) {
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rc = -EINVAL;
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goto out;
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}
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}
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data_len = to_process - sctx->count;
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in_sg = nx_build_sg_list(in_sg,
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(u8 *) data,
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&data_len,
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max_sg_len);
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if (data_len != to_process - sctx->count) {
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rc = -EINVAL;
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goto out;
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}
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) *
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sizeof(struct nx_sg);
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/* we've hit the nx chip previously and we're updating again,
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* so copy over the partial digest */
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if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
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memcpy(csbcpb->cpb.aes_xcbc.cv,
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csbcpb->cpb.aes_xcbc.out_cv_mac,
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AES_BLOCK_SIZE);
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}
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NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
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if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
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rc = -EINVAL;
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goto out;
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}
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->aes_ops));
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/* everything after the first update is continuation */
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NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
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total -= to_process;
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data += to_process - sctx->count;
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sctx->count = 0;
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in_sg = nx_ctx->in_sg;
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} while (leftover > AES_BLOCK_SIZE);
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/* copy the leftover back into the state struct */
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memcpy(sctx->buffer, data, leftover);
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sctx->count = leftover;
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out:
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spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
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return rc;
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}
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static int nx_xcbc_final(struct shash_desc *desc, u8 *out)
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{
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struct xcbc_state *sctx = shash_desc_ctx(desc);
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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struct nx_sg *in_sg, *out_sg;
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unsigned long irq_flags;
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int rc = 0;
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int len;
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spin_lock_irqsave(&nx_ctx->lock, irq_flags);
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if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
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/* we've hit the nx chip previously, now we're finalizing,
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* so copy over the partial digest */
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memcpy(csbcpb->cpb.aes_xcbc.cv,
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csbcpb->cpb.aes_xcbc.out_cv_mac, AES_BLOCK_SIZE);
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} else if (sctx->count == 0) {
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/*
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* we've never seen an update, so this is a 0 byte op. The
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* hardware cannot handle a 0 byte op, so just ECB to
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* generate the hash.
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*/
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rc = nx_xcbc_empty(desc, out);
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goto out;
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}
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/* final is represented by continuing the operation and indicating that
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* this is not an intermediate operation */
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
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len = sctx->count;
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in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *)sctx->buffer,
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&len, nx_ctx->ap->sglen);
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if (len != sctx->count) {
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rc = -EINVAL;
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goto out;
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}
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len = AES_BLOCK_SIZE;
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out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len,
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nx_ctx->ap->sglen);
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if (len != AES_BLOCK_SIZE) {
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rc = -EINVAL;
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goto out;
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}
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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if (!nx_ctx->op.outlen) {
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rc = -EINVAL;
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goto out;
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}
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->aes_ops));
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memcpy(out, csbcpb->cpb.aes_xcbc.out_cv_mac, AES_BLOCK_SIZE);
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out:
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spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct shash_alg nx_shash_aes_xcbc_alg = {
|
||
|
|
.digestsize = AES_BLOCK_SIZE,
|
||
|
|
.init = nx_xcbc_init,
|
||
|
|
.update = nx_xcbc_update,
|
||
|
|
.final = nx_xcbc_final,
|
||
|
|
.setkey = nx_xcbc_set_key,
|
||
|
|
.descsize = sizeof(struct xcbc_state),
|
||
|
|
.statesize = sizeof(struct xcbc_state),
|
||
|
|
.base = {
|
||
|
|
.cra_name = "xcbc(aes)",
|
||
|
|
.cra_driver_name = "xcbc-aes-nx",
|
||
|
|
.cra_priority = 300,
|
||
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
||
|
|
.cra_module = THIS_MODULE,
|
||
|
|
.cra_ctxsize = sizeof(struct nx_crypto_ctx),
|
||
|
|
.cra_init = nx_crypto_ctx_aes_xcbc_init2,
|
||
|
|
.cra_exit = nx_crypto_ctx_exit,
|
||
|
|
}
|
||
|
|
};
|