253 lines
8.2 KiB
C
253 lines
8.2 KiB
C
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// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2014 - 2021 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_config.h>
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#include <adf_gen2_dc.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_pfvf.h>
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#include "adf_dh895xcc_hw_data.h"
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#include "icp_qat_hw.h"
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#define ADF_DH895XCC_VF_MSK 0xFFFFFFFF
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/* Worker thread to service arbiter mappings */
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static const u32 thrd_to_arb_map[ADF_DH895XCC_MAX_ACCELENGINES] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
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};
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static struct adf_hw_device_class dh895xcc_class = {
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.name = ADF_DH895XCC_DEVICE_NAME,
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.type = DEV_DH895XCC,
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.instances = 0
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};
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static u32 get_accel_mask(struct adf_hw_device_data *self)
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{
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u32 fuses = self->fuses;
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return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
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ADF_DH895XCC_ACCELERATORS_MASK;
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}
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static u32 get_ae_mask(struct adf_hw_device_data *self)
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{
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u32 fuses = self->fuses;
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return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK;
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}
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static u32 get_misc_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_PMISC_BAR;
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}
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static u32 get_etr_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_ETR_BAR;
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}
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static u32 get_sram_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_SRAM_BAR;
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}
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static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
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{
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struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
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u32 capabilities;
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u32 legfuses;
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capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
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ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
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ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
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ICP_ACCEL_CAPABILITIES_CIPHER |
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ICP_ACCEL_CAPABILITIES_COMPRESSION;
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/* Read accelerator capabilities mask */
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pci_read_config_dword(pdev, ADF_DEVICE_LEGFUSE_OFFSET, &legfuses);
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/* A set bit in legfuses means the feature is OFF in this SKU */
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if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE) {
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
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}
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if (legfuses & ICP_ACCEL_MASK_PKE_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
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if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE) {
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capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
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}
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if (legfuses & ICP_ACCEL_MASK_COMPRESS_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
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return capabilities;
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}
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static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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{
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int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
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>> ADF_DH895XCC_FUSECTL_SKU_SHIFT;
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switch (sku) {
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case ADF_DH895XCC_FUSECTL_SKU_1:
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return DEV_SKU_1;
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case ADF_DH895XCC_FUSECTL_SKU_2:
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return DEV_SKU_2;
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case ADF_DH895XCC_FUSECTL_SKU_3:
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return DEV_SKU_3;
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case ADF_DH895XCC_FUSECTL_SKU_4:
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return DEV_SKU_4;
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default:
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return DEV_SKU_UNKNOWN;
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}
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return DEV_SKU_UNKNOWN;
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}
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static const u32 *adf_get_arbiter_mapping(void)
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{
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return thrd_to_arb_map;
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}
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static void enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
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{
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/* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */
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if (vf_mask & 0xFFFF) {
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u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
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& ~ADF_DH895XCC_ERR_MSK_VF2PF_L(vf_mask);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
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}
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/* Enable VF2PF Messaging Ints - VFs 16 through 31 per vf_mask[31:16] */
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if (vf_mask >> 16) {
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u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5)
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& ~ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val);
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}
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}
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static void disable_all_vf2pf_interrupts(void __iomem *pmisc_addr)
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{
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u32 val;
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/* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */
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val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
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| ADF_DH895XCC_ERR_MSK_VF2PF_L(ADF_DH895XCC_VF_MSK);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
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/* Disable VF2PF interrupts for VFs 16 through 31 per vf_mask[31:16] */
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val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5)
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| ADF_DH895XCC_ERR_MSK_VF2PF_U(ADF_DH895XCC_VF_MSK);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val);
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}
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static u32 disable_pending_vf2pf_interrupts(void __iomem *pmisc_addr)
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{
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u32 sources, pending, disabled;
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u32 errsou3, errmsk3;
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u32 errsou5, errmsk5;
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/* Get the interrupt sources triggered by VFs */
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errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3);
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errsou5 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU5);
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sources = ADF_DH895XCC_ERR_REG_VF2PF_L(errsou3)
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| ADF_DH895XCC_ERR_REG_VF2PF_U(errsou5);
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if (!sources)
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return 0;
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/* Get the already disabled interrupts */
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errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3);
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errmsk5 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5);
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disabled = ADF_DH895XCC_ERR_REG_VF2PF_L(errmsk3)
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| ADF_DH895XCC_ERR_REG_VF2PF_U(errmsk5);
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pending = sources & ~disabled;
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if (!pending)
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return 0;
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/* Due to HW limitations, when disabling the interrupts, we can't
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* just disable the requested sources, as this would lead to missed
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* interrupts if sources changes just before writing to ERRMSK3 and
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* ERRMSK5.
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* To work around it, disable all and re-enable only the sources that
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* are not in vf_mask and were not already disabled. Re-enabling will
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* trigger a new interrupt for the sources that have changed in the
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* meantime, if any.
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*/
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errmsk3 |= ADF_DH895XCC_ERR_MSK_VF2PF_L(ADF_DH895XCC_VF_MSK);
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errmsk5 |= ADF_DH895XCC_ERR_MSK_VF2PF_U(ADF_DH895XCC_VF_MSK);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5);
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errmsk3 &= ADF_DH895XCC_ERR_MSK_VF2PF_L(sources | disabled);
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errmsk5 &= ADF_DH895XCC_ERR_MSK_VF2PF_U(sources | disabled);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5);
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/* Return the sources of the (new) interrupt(s) */
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return pending;
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}
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static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
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{
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adf_gen2_cfg_iov_thds(accel_dev, enable,
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ADF_DH895XCC_AE2FUNC_MAP_GRP_A_NUM_REGS,
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ADF_DH895XCC_AE2FUNC_MAP_GRP_B_NUM_REGS);
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}
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void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class = &dh895xcc_class;
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hw_data->instance_id = dh895xcc_class.instances++;
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hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;
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hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
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hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;
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hw_data->num_logical_accel = 1;
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hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
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hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_gen2_enable_error_correction;
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hw_data->get_accel_mask = get_accel_mask;
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hw_data->get_ae_mask = get_ae_mask;
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hw_data->get_accel_cap = get_accel_cap;
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hw_data->get_num_accels = adf_gen2_get_num_accels;
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hw_data->get_num_aes = adf_gen2_get_num_aes;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_admin_info = adf_gen2_get_admin_info;
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hw_data->get_arb_info = adf_gen2_get_arb_info;
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hw_data->get_sram_bar_id = get_sram_bar_id;
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hw_data->get_sku = get_sku;
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hw_data->fw_name = ADF_DH895XCC_FW;
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hw_data->fw_mmp_name = ADF_DH895XCC_MMP;
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hw_data->init_admin_comms = adf_init_admin_comms;
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hw_data->exit_admin_comms = adf_exit_admin_comms;
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hw_data->configure_iov_threads = configure_iov_threads;
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hw_data->send_admin_init = adf_send_admin_init;
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hw_data->init_arb = adf_init_arb;
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hw_data->exit_arb = adf_exit_arb;
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hw_data->get_arb_mapping = adf_get_arbiter_mapping;
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hw_data->enable_ints = adf_gen2_enable_ints;
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hw_data->reset_device = adf_reset_sbr;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->dev_config = adf_gen2_dev_config;
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adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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hw_data->pfvf_ops.enable_vf2pf_interrupts = enable_vf2pf_interrupts;
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hw_data->pfvf_ops.disable_all_vf2pf_interrupts = disable_all_vf2pf_interrupts;
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hw_data->pfvf_ops.disable_pending_vf2pf_interrupts = disable_pending_vf2pf_interrupts;
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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adf_gen2_init_dc_ops(&hw_data->dc_ops);
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}
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void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class->instances--;
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}
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