255 lines
7.2 KiB
C
255 lines
7.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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* Copyright 2018 Angelo Dureghello <angelo@sysam.it>
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*/
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#ifndef _FSL_EDMA_COMMON_H_
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#define _FSL_EDMA_COMMON_H_
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#include <linux/dma-direction.h>
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#include <linux/platform_device.h>
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#include "virt-dma.h"
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#define EDMA_CR_EDBG BIT(1)
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#define EDMA_CR_ERCA BIT(2)
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#define EDMA_CR_ERGA BIT(3)
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#define EDMA_CR_HOE BIT(4)
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#define EDMA_CR_HALT BIT(5)
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#define EDMA_CR_CLM BIT(6)
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#define EDMA_CR_EMLM BIT(7)
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#define EDMA_CR_ECX BIT(16)
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#define EDMA_CR_CX BIT(17)
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#define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))
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#define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))
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#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
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#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
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#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
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#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
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#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
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#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
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#define EDMA_TCD_ATTR_DSIZE_8BIT 0
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#define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0)
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#define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1)
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#define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1))
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#define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(2) | BIT(0))
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#define EDMA_TCD_ATTR_SSIZE_8BIT 0
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#define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8)
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#define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8)
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#define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8)
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#define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8)
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#define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0))
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#define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0))
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#define EDMA_TCD_CSR_START BIT(0)
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#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
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#define EDMA_TCD_CSR_INT_HALF BIT(2)
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#define EDMA_TCD_CSR_D_REQ BIT(3)
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#define EDMA_TCD_CSR_E_SG BIT(4)
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#define EDMA_TCD_CSR_E_LINK BIT(5)
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#define EDMA_TCD_CSR_ACTIVE BIT(6)
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#define EDMA_TCD_CSR_DONE BIT(7)
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#define EDMAMUX_CHCFG_DIS 0x0
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#define EDMAMUX_CHCFG_ENBL 0x80
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#define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
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#define DMAMUX_NR 2
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#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
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enum fsl_edma_pm_state {
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RUNNING = 0,
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SUSPENDED,
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};
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struct fsl_edma_hw_tcd {
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__le32 saddr;
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__le16 soff;
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__le16 attr;
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__le32 nbytes;
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__le32 slast;
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__le32 daddr;
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__le16 doff;
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__le16 citer;
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__le32 dlast_sga;
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__le16 csr;
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__le16 biter;
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};
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/*
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* These are iomem pointers, for both v32 and v64.
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*/
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struct edma_regs {
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void __iomem *cr;
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void __iomem *es;
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void __iomem *erqh;
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void __iomem *erql; /* aka erq on v32 */
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void __iomem *eeih;
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void __iomem *eeil; /* aka eei on v32 */
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void __iomem *seei;
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void __iomem *ceei;
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void __iomem *serq;
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void __iomem *cerq;
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void __iomem *cint;
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void __iomem *cerr;
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void __iomem *ssrt;
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void __iomem *cdne;
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void __iomem *inth;
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void __iomem *intl;
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void __iomem *errh;
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void __iomem *errl;
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struct fsl_edma_hw_tcd __iomem *tcd;
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};
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struct fsl_edma_sw_tcd {
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dma_addr_t ptcd;
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struct fsl_edma_hw_tcd *vtcd;
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};
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struct fsl_edma_chan {
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struct virt_dma_chan vchan;
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enum dma_status status;
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enum fsl_edma_pm_state pm_state;
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bool idle;
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u32 slave_id;
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struct fsl_edma_engine *edma;
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struct fsl_edma_desc *edesc;
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struct dma_slave_config cfg;
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u32 attr;
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bool is_sw;
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struct dma_pool *tcd_pool;
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dma_addr_t dma_dev_addr;
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u32 dma_dev_size;
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enum dma_data_direction dma_dir;
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char chan_name[16];
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};
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struct fsl_edma_desc {
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struct virt_dma_desc vdesc;
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struct fsl_edma_chan *echan;
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bool iscyclic;
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enum dma_transfer_direction dirn;
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unsigned int n_tcds;
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struct fsl_edma_sw_tcd tcd[];
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};
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enum edma_version {
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v1, /* 32ch, Vybrid, mpc57x, etc */
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v2, /* 64ch Coldfire */
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v3, /* 32ch, i.mx7ulp */
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};
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struct fsl_edma_drvdata {
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enum edma_version version;
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u32 dmamuxs;
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bool has_dmaclk;
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bool mux_swap;
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int (*setup_irq)(struct platform_device *pdev,
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struct fsl_edma_engine *fsl_edma);
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};
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struct fsl_edma_engine {
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struct dma_device dma_dev;
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void __iomem *membase;
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void __iomem *muxbase[DMAMUX_NR];
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struct clk *muxclk[DMAMUX_NR];
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struct clk *dmaclk;
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struct mutex fsl_edma_mutex;
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const struct fsl_edma_drvdata *drvdata;
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u32 n_chans;
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int txirq;
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int errirq;
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bool big_endian;
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struct edma_regs regs;
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struct fsl_edma_chan chans[];
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};
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/*
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* R/W functions for big- or little-endian registers:
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* The eDMA controller's endian is independent of the CPU core's endian.
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* For the big-endian IP module, the offset for 8-bit or 16-bit registers
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* should also be swapped opposite to that in little-endian IP.
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*/
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static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
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{
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if (edma->big_endian)
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return ioread32be(addr);
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else
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return ioread32(addr);
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}
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static inline void edma_writeb(struct fsl_edma_engine *edma,
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u8 val, void __iomem *addr)
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{
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/* swap the reg offset for these in big-endian mode */
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if (edma->big_endian)
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iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
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else
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iowrite8(val, addr);
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}
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static inline void edma_writew(struct fsl_edma_engine *edma,
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u16 val, void __iomem *addr)
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{
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/* swap the reg offset for these in big-endian mode */
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if (edma->big_endian)
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iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
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else
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iowrite16(val, addr);
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}
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static inline void edma_writel(struct fsl_edma_engine *edma,
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u32 val, void __iomem *addr)
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{
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if (edma->big_endian)
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iowrite32be(val, addr);
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else
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iowrite32(val, addr);
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}
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static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct fsl_edma_chan, vchan.chan);
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}
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static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct fsl_edma_desc, vdesc);
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}
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void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
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void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
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unsigned int slot, bool enable);
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void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
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int fsl_edma_terminate_all(struct dma_chan *chan);
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int fsl_edma_pause(struct dma_chan *chan);
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int fsl_edma_resume(struct dma_chan *chan);
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int fsl_edma_slave_config(struct dma_chan *chan,
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struct dma_slave_config *cfg);
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enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *txstate);
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struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction direction,
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unsigned long flags);
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struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context);
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struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
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struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
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size_t len, unsigned long flags);
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void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
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void fsl_edma_issue_pending(struct dma_chan *chan);
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int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
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void fsl_edma_free_chan_resources(struct dma_chan *chan);
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void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
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void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
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#endif /* _FSL_EDMA_COMMON_H_ */
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